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Josh-Tsaiquinchou77
Josh-Tsai
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quinchou77
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fwk: split the 4 usbc ports configuration to a new file
As title, split the 4 usbc ports configuration to a new file. Project can override the initial state by itself. BRANCH=fwk-main BUG=None TEST=PD function is workable on the Marigold and Lotus units Signed-off-by: Josh-Tsai <josh_tsai@compal.com> (cherry picked from commit dfb82d1)
1 parent 73bccbf commit 05c9bba

6 files changed

Lines changed: 88 additions & 60 deletions

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‎zephyr/program/framework/CMakeLists.txt‎

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -58,10 +58,8 @@ if(DEFINED CONFIG_BOARD_LOTUS)
5858
"lotus/src/thermal.c"
5959
"lotus/src/gpu_configuration.c"
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"lotus/src/gpu_f75303.c"
61+
"src/usbc_4port_config.c"
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"src/temperature_filter.c"
62-
63-
64-
6563
)
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zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_AMD_STT
6765
"lotus/src/stt.c")
@@ -78,8 +76,9 @@ if(DEFINED CONFIG_BOARD_AZALEA)
7876
"azalea/src/cpu_power.c"
7977
"azalea/src/input_module.c"
8078
"azalea/src/power_sequence.c"
81-
"src/keyboard_customization_13.c"
8279
"azalea/src/project_diagnostics.c"
80+
"src/usbc_4port_config.c"
81+
"src/keyboard_customization_13.c"
8382
)
8483
zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_AMD_STT
8584
"azalea/src/stt.c")
@@ -99,6 +98,8 @@ if(DEFINED CONFIG_BOARD_MARIGOLD)
9998
"marigold/src/project_diagnostics.c"
10099
"marigold/src/temperature.c"
101100
"marigold/src/thermal.c"
101+
"marigold/src/usbc.c"
102+
"src/usbc_4port_config.c"
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)
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104105
endif()

‎zephyr/program/framework/include/cypress_pd_common.h‎

Lines changed: 0 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -11,15 +11,6 @@
1111
#include "usb_pd.h"
1212

1313
/* 7 bit address */
14-
/* TODO: create a i2c ccg yaml to define the i2c address */
15-
#ifdef CONFIG_PD_CHIP_CCG8
16-
#define CCG_I2C_CHIP0 0x42
17-
#define CCG_I2C_CHIP1 0x40
18-
#elif defined(CONFIG_PD_CHIP_CCG6)
19-
#define CCG_I2C_CHIP0 0x08
20-
#define CCG_I2C_CHIP1 0x40
21-
#endif
22-
2314
#define PRODUCT_ID CONFIG_PD_USB_PID
2415
#define VENDOR_ID 0x32ac
2516

‎zephyr/program/framework/marigold/src/usbc.c‎

Lines changed: 23 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,23 @@
1+
/* Copyright 2024 The ChromiumOS Authors
2+
* Use of this source code is governed by a BSD-style license that can be
3+
* found in the LICENSE file.
4+
*/
5+
6+
#include "ec_commands.h"
7+
#include "hooks.h"
8+
#include "cypress_pd_common.h"
9+
10+
static void board_change_cypd_init_state(void)
11+
{
12+
int controller;
13+
14+
/*
15+
* The PD1 firmware adds the hard code to delay 415ms, in this duration,
16+
* the PD chip cannot communicate via i2c.
17+
* EC changes the initial state to CCG_STATE_WAIT_STABLE to wait the PD
18+
* exits the delay.
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*/
20+
for (controller = 0; controller < PD_CHIP_COUNT; controller++)
21+
pd_chip_config[controller].state = CCG_STATE_WAIT_STABLE;
22+
}
23+
DECLARE_HOOK(HOOK_INIT, board_change_cypd_init_state, HOOK_PRIO_DEFAULT);

‎zephyr/program/framework/src/cypress_pd_common.c‎

Lines changed: 0 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -38,44 +38,6 @@
3838
#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
3939
#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
4040

41-
#undef CCG_INIT_STATE
42-
#ifdef CONFIG_PD_CHIP_CCG6
43-
#define CCG_INIT_STATE CCG_STATE_WAIT_STABLE
44-
#else
45-
#define CCG_INIT_STATE CCG_STATE_POWER_ON
46-
#endif
47-
48-
struct pd_chip_config_t pd_chip_config[] = {
49-
[PD_CHIP_0] = {
50-
.i2c_port = I2C_PORT_PD_MCU0,
51-
.addr_flags = CCG_I2C_CHIP0 | I2C_FLAG_ADDR16_LITTLE_ENDIAN,
52-
.state = CCG_INIT_STATE,
53-
.gpio = GPIO_EC_PD_INTA_L,
54-
},
55-
[PD_CHIP_1] = {
56-
.i2c_port = I2C_PORT_PD_MCU1,
57-
.addr_flags = CCG_I2C_CHIP1 | I2C_FLAG_ADDR16_LITTLE_ENDIAN,
58-
.state = CCG_INIT_STATE,
59-
.gpio = GPIO_EC_PD_INTB_L,
60-
},
61-
};
62-
BUILD_ASSERT(ARRAY_SIZE(pd_chip_config) == PD_CHIP_COUNT);
63-
64-
struct pd_port_current_state_t pd_port_states[] = {
65-
[PD_PORT_0] = {
66-
67-
},
68-
[PD_PORT_1] = {
69-
70-
},
71-
[PD_PORT_2] = {
72-
73-
},
74-
[PD_PORT_3] = {
75-
76-
}
77-
};
78-
7941
struct alert_msg_t alert_rx[CONFIG_USB_PD_PORT_MAX_COUNT];
8042

8143
static int prev_charge_port = -1;

‎zephyr/program/framework/src/ucsi.c‎

Lines changed: 0 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -32,15 +32,6 @@
3232
#define CCI_ERROR_FLAG BIT(30)
3333
#define CCI_COMPLETE_FLAG BIT(31)
3434

35-
struct pd_chip_ucsi_info_t pd_chip_ucsi_info[] = {
36-
[PD_CHIP_0] = {
37-
38-
},
39-
[PD_CHIP_1] = {
40-
41-
}
42-
};
43-
4435
static int ucsi_debug_enable;
4536
static uint8_t s0ix_connector_change_indicator;
4637
static bool read_complete;

‎zephyr/program/framework/src/usbc_4port_config.c‎

Lines changed: 60 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,60 @@
1+
/* Copyright 2024 The ChromiumOS Authors
2+
* Use of this source code is governed by a BSD-style license that can be
3+
* found in the LICENSE file.
4+
*/
5+
6+
#include "gpio.h"
7+
#include "i2c.h"
8+
#include "cypress_pd_common.h"
9+
10+
/* 7 bit address */
11+
/* TODO: create a i2c ccg yaml to define the i2c address */
12+
#ifdef CONFIG_PD_CHIP_CCG8
13+
#define CCG_I2C_CHIP0 0x42
14+
#define CCG_I2C_CHIP1 0x40
15+
#elif defined(CONFIG_PD_CHIP_CCG6)
16+
#define CCG_I2C_CHIP0 0x08
17+
#define CCG_I2C_CHIP1 0x40
18+
#endif
19+
20+
struct pd_chip_config_t pd_chip_config[] = {
21+
[PD_CHIP_0] = {
22+
.i2c_port = I2C_PORT_PD_MCU0,
23+
.addr_flags = CCG_I2C_CHIP0 | I2C_FLAG_ADDR16_LITTLE_ENDIAN,
24+
.state = CCG_STATE_POWER_ON,
25+
.gpio = GPIO_EC_PD_INTA_L,
26+
},
27+
[PD_CHIP_1] = {
28+
.i2c_port = I2C_PORT_PD_MCU1,
29+
.addr_flags = CCG_I2C_CHIP1 | I2C_FLAG_ADDR16_LITTLE_ENDIAN,
30+
.state = CCG_STATE_POWER_ON,
31+
.gpio = GPIO_EC_PD_INTB_L,
32+
},
33+
};
34+
BUILD_ASSERT(ARRAY_SIZE(pd_chip_config) == CONFIG_PLATFORM_EC_PD_CHIP_MAX_COUNT);
35+
36+
struct pd_port_current_state_t pd_port_states[] = {
37+
[PD_PORT_0] = {
38+
39+
},
40+
[PD_PORT_1] = {
41+
42+
},
43+
[PD_PORT_2] = {
44+
45+
},
46+
[PD_PORT_3] = {
47+
48+
}
49+
};
50+
BUILD_ASSERT(ARRAY_SIZE(pd_port_states) == CONFIG_USB_PD_PORT_MAX_COUNT);
51+
52+
struct pd_chip_ucsi_info_t pd_chip_ucsi_info[] = {
53+
[PD_CHIP_0] = {
54+
55+
},
56+
[PD_CHIP_1] = {
57+
58+
}
59+
};
60+
BUILD_ASSERT(ARRAY_SIZE(pd_chip_ucsi_info) == CONFIG_PLATFORM_EC_PD_CHIP_MAX_COUNT);

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