fwk: modified the PD code to support one PD chip

Remove the hard code and use the for-loop to update the PD status.

BRANCH=fwk-main
BUG=None
TEST=Marigold four type-c ports are workable
TEST=Marigold right side type-c ports are workable if the PD chip is to 1
TEST=Either support 1 PD chip or 2 PD chips the error recovery feature is workable
TEST=Either support 1 PD chip or 2 PD chips that can display the PD version in the setup menu

Signed-off-by: Josh-Tsai <josh_tsai@compal.com>
(cherry picked from commit bb8e00c)

Author: Josh-Tsai

zephyr/program/framework/Kconfig

@@ -104,6 +104,13 @@ config PD_CCG8_CUSTOMIZE_BATT_MESSAGE
 	    Enable customize battery response for GRL test, EC will write specific
 		register 0x4f to PD for GET_BATTERY_CAP and GET_BATTERY_STATUS.
 
+config PLATFORM_EC_PD_CHIP_MAX_COUNT
+	int "The maximum PD chips"
+	default 2
+	help
+		We would like to design the PD function more flexible.
+		Use this configuration to set the maximum PD chip with mainboard design.
+
 config PD_COMMON_VBUS_CONTROL
 	bool "Enable CCG common vbus control"
 	help

zephyr/program/framework/include/cypress_pd_common.h

@@ -233,6 +233,9 @@
 /************************************************/
 #define PORT_TO_CONTROLLER(x) ((x) >> 1)
 #define PORT_TO_CONTROLLER_PORT(x) ((x) & 0x01)
+#define PORTS_PER_CONTROLLER 2
+#define CONTROLLER_PORT_TO_CHARGE_PORT(controller, port) \
+	(controller * PORTS_PER_CONTROLLER + port)
 
 /************************************************/
 /*  CCG6 special setting                        */
@@ -489,18 +492,18 @@ enum pd_port_role {
 	PORT_DUALROLE
 };
 
+#define PD_CHIP_COUNT CONFIG_PLATFORM_EC_PD_CHIP_MAX_COUNT
 enum pd_chip {
 	PD_CHIP_0,
 	PD_CHIP_1,
-	PD_CHIP_COUNT
 };
 
+#define PD_PORT_COUNT CONFIG_USB_PD_PORT_MAX_COUNT
 enum pd_port {
 	PD_PORT_0,
 	PD_PORT_1,
 	PD_PORT_2,
 	PD_PORT_3,
-	PD_PORT_COUNT
 };
 
 enum pd_progress {
@@ -977,4 +980,12 @@ int get_pd_alt_mode_status(int port);
  */
 void perform_error_recovery(int controller);
 
+/**
+ * CYPD interrupt pin control.
+ *
+ * @param controller The port number for which to retrieve the state.
+ * @param enable_ndisable enable/disable interrupt.
+ */
+void cypd_enable_interrupt(int controller, int enable_ndisable);
+
 #endif /* __CROS_EC_CYPRESS_PD_COMMON_H */

zephyr/program/framework/program.conf

@@ -6,6 +6,8 @@ CONFIG_PLATFORM_EC=y
 CONFIG_CROS_EC=y
 CONFIG_SHIMMED_TASKS=y
 CONFIG_SYSCON=y
+CONFIG_ASSERT=y
+
 # Not sure what overrides the default in zephyr/app/ec/Kconfig. We shouldn't have to override it here
 CONFIG_NUM_PREEMPT_PRIORITIES=28
 CONFIG_SYSTEM_WORKQUEUE_PRIORITY=27

zephyr/program/framework/src/board_host_command.c

@@ -83,6 +83,7 @@ static enum ec_status flash_notified(struct host_cmd_handler_args *args)
 {
 
 	const struct ec_params_flash_notified *p = args->params;
+	int controller;
 
 	switch (p->flags & 0x03) {
 	case FLASH_FIRMWARE_START:
@@ -91,8 +92,9 @@ static enum ec_status flash_notified(struct host_cmd_handler_args *args)
 		gpio_disable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_lid_open));
 
 		if ((p->flags & FLASH_FLAG_PD) == FLASH_FLAG_PD) {
-			gpio_disable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_pd_chip0_interrupt));
-			gpio_disable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_pd_chip1_interrupt));
+			for (controller = 0; controller < PD_CHIP_COUNT; controller++)
+				cypd_enable_interrupt(controller, false);
+
 			set_pd_fw_update(true);
 		}
 	case FLASH_ACCESS_SPI:
@@ -101,9 +103,12 @@ static enum ec_status flash_notified(struct host_cmd_handler_args *args)
 	case FLASH_FIRMWARE_DONE:
 		CPRINTS("Flash done, flags:0x%02x", p->flags);
 		gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_powerbtn));
-		gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_pd_chip0_interrupt));
-		gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_pd_chip1_interrupt));
+#if DT_NODE_EXISTS(DT_NODELABEL(gpio_lid_sw_l))
+		/* TODO: should refactor this for each prjects */
 		gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_lid_open));
+#endif
+		for (controller = 0; controller < PD_CHIP_COUNT; controller++)
+			cypd_enable_interrupt(controller, true);
 
 		set_pd_fw_update(false);
 		/* resetup PD controllers */

zephyr/program/framework/src/cypd_ccg6.c

@@ -45,6 +45,8 @@ int cypd_write_reg8_wait_ack(int controller, int reg, int data)
 	int expected_ack_mask = 0;
 	const struct gpio_dt_spec *intr = gpio_get_dt_spec(pd_chip_config[controller].gpio);
 
+	__ASSERT(controller < PD_CHIP_COUNT, "Invalid PD chip controller id in %s.", __func__);
+
 	if (reg < 0x1000) {
 		expected_ack_mask = CCG_DEV_INTR;
 		cmd_port = -1;
@@ -180,6 +182,8 @@ int cypd_setup(int controller)
 	};
 	BUILD_ASSERT(ARRAY_SIZE(cypd_setup_cmds) == CYPD_SETUP_CMDS_LEN);
 
+	__ASSERT(controller < PD_CHIP_COUNT, "Invalid PD chip controller id in %s.", __func__);
+
 	/* Make sure the interrupt is not asserted before we start */
 	if (gpio_pin_get_dt(intr) == 0) {
 		rv = cypd_get_int(controller, &data);
@@ -214,11 +218,26 @@ int cypd_setup(int controller)
 void cypd_update_ac_status(int controller)
 {
 	CPRINTS("Check C%d AC status!", controller);
+
+	__ASSERT(controller < PD_CHIP_COUNT, "Invalid PD chip controller id in %s.", __func__);
+
 	if (cypd_write_reg8_wait_ack(controller,
 		CCG_CUST_C_CTRL_CONTROL_REG, CCG6_AC_AT_PORT))
 		CPRINTS("CYPD Read AC status fail");
 }
 
+__maybe_unused static bool are_cypd_chips_ready(void)
+{
+	int controller;
+
+	for (controller = 0; controller < PD_CHIP_COUNT; controller++) {
+		if (pd_chip_config[controller].state != CCG_STATE_READY)
+			return EC_ERROR_BUSY;
+	}
+
+	return EC_SUCCESS;
+}
+
 __override void cypd_customize_app_setup(int controller)
 {
 	/* After cypd setup complete, check the AC status */
@@ -235,8 +254,7 @@ int check_power_on_port(void)
 {
 	int port;
 	/* only read CYPD when it ready */
-	if (!(pd_chip_config[0].state == CCG_STATE_READY &&
-		pd_chip_config[1].state == CCG_STATE_READY)) {
+	if (!are_cypd_chips_ready()) {
 		CPRINTS("CYPD not ready, just delay 100ms to wait");
 		crec_msleep(100);
 	}
@@ -315,6 +333,8 @@ void update_system_power_state(int controller)
 	/* CCG6 does not support power state G3, just for initial state */
 	static uint8_t pre_state = CCG_POWERSTATE_G3;
 
+	__ASSERT(controller < PD_CHIP_COUNT, "Invalid PD chip controller id in %s.", __func__);
+
 	switch (ps) {
 	case POWER_G3:
 	case POWER_S5G3:
@@ -368,6 +388,8 @@ void enable_compliance_mode(int controller)
 	uint32_t debug_register = 0xD0000000;
 	int debug_ctl = 0x0100;
 
+	__ASSERT(controller < PD_CHIP_COUNT, "Invalid PD chip controller id in %s.", __func__);
+
 	/* Write 0xD0000000 to address 0x0048 */
 	rv = cypd_write_reg_block(controller, CCG_ICL_BB_RETIMER_DAT_REG,
 			(void *) &debug_register, 4);
@@ -386,6 +408,8 @@ void disable_compliance_mode(int controller)
 	uint32_t debug_register = 0x00000000;
 	int debug_ctl = 0x0000;
 
+	__ASSERT(controller < PD_CHIP_COUNT, "Invalid PD chip controller id in %s.", __func__);
+
 	/* Write 0x00000000 to address 0x0048 */
 	rv = cypd_write_reg_block(controller, CCG_ICL_BB_RETIMER_DAT_REG,
 			(void *) &debug_register, 4);
@@ -404,6 +428,8 @@ void entry_tbt_mode(int controller)
 	uint8_t force_tbt_mode = 0x01;
 	int debug_ctl = 0x0100;
 
+	__ASSERT(controller < PD_CHIP_COUNT, "Invalid PD chip controller id in %s.", __func__);
+
 	/* Write 0x0100 to address 0x0046 */
 	rv = cypd_write_reg16(controller, CCG_ICL_BB_RETIMER_CMD_REG, debug_ctl);
 	if (rv != EC_SUCCESS)
@@ -421,6 +447,8 @@ void exit_tbt_mode(int controller)
 	uint8_t force_tbt_mode = 0x00;
 	int debug_ctl = 0x0000;
 
+	__ASSERT(controller < PD_CHIP_COUNT, "Invalid PD chip controller id in %s.", __func__);
+
 	/* Write 0x00 to address 0x0040 */
 	rv = cypd_write_reg8(controller, CCG_ICL_CTRL_REG, force_tbt_mode);
 	if (rv != EC_SUCCESS)
@@ -437,6 +465,8 @@ int check_tbt_mode(int controller)
 	int rv;
 	int data;
 
+	__ASSERT(controller < PD_CHIP_COUNT, "Invalid PD chip controller id in %s.", __func__);
+
 	rv = cypd_read_reg8(controller, CCG_ICL_STS_REG, &data);
 	if (rv != EC_SUCCESS)
 		CPRINTS("Read CYP5525_ICL_STS_REG fail");
@@ -462,10 +492,8 @@ void cypd_customize_battery_cap(void)
 		battery_get_disconnect_state();
 
 	/* only send status when PD ready */
-	if (!(pd_chip_config[0].state == CCG_STATE_READY &&
-		pd_chip_config[1].state == CCG_STATE_READY)) {
+	if (!are_cypd_chips_ready())
 		return;
-	}
 
 	if (!battery_can_discharge) {
 		cypd_batt_update = false;
@@ -518,10 +546,8 @@ void cypd_customize_battery_status(void)
 	battery_get_params(&batt);
 
 	/* only send status when PD ready */
-	if (!(pd_chip_config[0].state == CCG_STATE_READY &&
-		pd_chip_config[1].state == CCG_STATE_READY)) {
+	if (!are_cypd_chips_ready())
 		return;
-	}
 
 	/* only update data when soc change */
 	if (batt.state_of_charge == pd_batt_soc)

zephyr/program/framework/src/cypd_ccg8.c

@@ -195,6 +195,8 @@ void update_system_power_state(int controller)
 {
 	enum power_state ps = power_get_state();
 
+	__ASSERT(controller < PD_CHIP_COUNT, "Invalid PD chip controller id in %s.", __func__);
+
 	switch (ps) {
 	case POWER_G3:
 	case POWER_S5G3:
@@ -577,6 +579,8 @@ void cypd_update_epr_state(int controller, int port, int response_len)
 	uint16_t addr_flags = pd_chip_config[controller].addr_flags;
 	int port_idx = (controller << 1) + port;
 
+	__ASSERT(controller < PD_CHIP_COUNT, "Invalid PD chip controller id in %s.", __func__);
+
 	rv = i2c_read_offset16_block(i2c_port, addr_flags,
 		CCG_READ_DATA_MEMORY_REG(port, 0), data, MIN(response_len, 16));