fwk: refactor UCSI port and PD port map

Some project's pd port order is different, we need to switch
the port order for UCSI. Refactor UCSI port and PD port map for the
further project.

BRANCH=fwk-main
BUG=https://app.clickup.com/t/86eqhvxm6
TEST= use console cmd "cypdctl ucsi 1" enable UCSI log and check
port is match on marigold unit.

Signed-off-by: LeilaCY-Lin <LeilaCY_Lin@compal.com>
(cherry picked from commit 64c85ed)

Author: LeilaCY-Lin

zephyr/program/framework/src/ucsi_port_13_16.c

@@ -0,0 +1,27 @@
+/*
+ * Copyright 2024 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ucsi.h"
+#include "cypress_pd_common.h"
+
+enum ucsi_port {
+	UCSI_PORT_1,
+	UCSI_PORT_2,
+	UCSI_PORT_3,
+	UCSI_PORT_4,
+};
+
+struct ucsi_to_pd_port_map ucsi_pd_port_map[] = {
+	[UCSI_PORT_1] = {.pd_controller = PD_CHIP_0,
+					 .pd_controller_port = PD_CHIP_UCSI_CONNECTOR_1},
+	[UCSI_PORT_2] = {.pd_controller = PD_CHIP_0,
+					 .pd_controller_port = PD_CHIP_UCSI_CONNECTOR_2},
+	[UCSI_PORT_3] = {.pd_controller = PD_CHIP_1,
+					 .pd_controller_port = PD_CHIP_UCSI_CONNECTOR_1},
+	[UCSI_PORT_4] = {.pd_controller = PD_CHIP_1,
+					 .pd_controller_port = PD_CHIP_UCSI_CONNECTOR_2},
+};
+BUILD_ASSERT(ARRAY_SIZE(ucsi_pd_port_map) == CONFIG_USB_PD_PORT_MAX_COUNT);