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Merge tag 'drm-fixes-2020-12-04' of git://anongit.freedesktop.org/drm/drm
Pull drm fixes from Dave Airlie: "This week's regular fixes. i915 has fixes for a few races, use-after-free, and gpu hangs. Tegra just has some minor fixes that I didn't see much point in hanging on to. The nouveau fix is for all pre-nv50 cards and was reported a few times. Otherwise it's just some amdgpu, and a few misc fixes. Summary: amdgpu: - SMU11 manual fan fix - Renoir display clock fix - VCN3 dynamic powergating fix i915: - Program mocs:63 for cache eviction on gen9 (Chris) - Protect context lifetime with RCU (Chris) - Split the breadcrumb spinlock between global and contexts (Chris) - Retain default context state across shrinking (Venkata) - Limit frequency drop to RPe on parking (Chris) - Return earlier from intel_modeset_init() without display (Jani) - Defer initial modeset until after GGTT is initialized (Chris) nouveau: - pre-nv50 regression fix rockchip: - uninitialised LVDS property fix omap: - bridge fix panel: - race fix mxsfb: - fence sync fix - modifiers fix tegra: - idr init fix - sor fixes - output/of cleanup fix" * tag 'drm-fixes-2020-12-04' of git://anongit.freedesktop.org/drm/drm: (22 commits) drm/amdgpu/vcn3.0: remove old DPG workaround drm/amdgpu/vcn3.0: stall DPG when WPTR/RPTR reset drm/amd/display: Init clock value by current vbios CLKs drm/amdgpu/pm/smu11: Fix fan set speed bug drm/i915/display: Defer initial modeset until after GGTT is initialised drm/i915/display: return earlier from intel_modeset_init() without display drm/i915/gt: Limit frequency drop to RPe on parking drm/i915/gt: Retain default context state across shrinking drm/i915/gt: Split the breadcrumb spinlock between global and contexts drm/i915/gt: Protect context lifetime with RCU drm/i915/gt: Program mocs:63 for cache eviction on gen9 drm/omap: sdi: fix bridge enable/disable drm/panel: sony-acx565akm: Fix race condition in probe drm/rockchip: Avoid uninitialized use of endpoint id in LVDS drm/tegra: sor: Disable clocks on error in tegra_sor_init() drm/nouveau: make sure ret is initialized in nouveau_ttm_io_mem_reserve drm: mxsfb: Implement .format_mod_supported drm: mxsfb: fix fence synchronization drm/tegra: output: Do not put OF node twice drm/tegra: replace idr_init() by idr_init_base() ...
2 parents bbe2ba0 + de9b485 commit e87297f

20 files changed

Lines changed: 233 additions & 185 deletions

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‎drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c‎

Lines changed: 19 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1011,6 +1011,11 @@ static int vcn_v3_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo
10111011
tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
10121012
WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_CNTL, tmp);
10131013

1014+
/* Stall DPG before WPTR/RPTR reset */
1015+
WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),
1016+
UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,
1017+
~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
1018+
10141019
/* set the write pointer delay */
10151020
WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR_CNTL, 0);
10161021

@@ -1033,6 +1038,10 @@ static int vcn_v3_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo
10331038
WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR,
10341039
lower_32_bits(ring->wptr));
10351040

1041+
/* Unstall DPG */
1042+
WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),
1043+
0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
1044+
10361045
return 0;
10371046
}
10381047

@@ -1556,23 +1565,31 @@ static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev,
15561565
UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,
15571566
UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
15581567

1568+
/* Stall DPG before WPTR/RPTR reset */
1569+
WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),
1570+
UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,
1571+
~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
1572+
15591573
/* Restore */
15601574
ring = &adev->vcn.inst[inst_idx].ring_enc[0];
1575+
ring->wptr = 0;
15611576
WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr);
15621577
WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
15631578
WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4);
15641579
WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
15651580
WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
15661581

15671582
ring = &adev->vcn.inst[inst_idx].ring_enc[1];
1583+
ring->wptr = 0;
15681584
WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr);
15691585
WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
15701586
WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4);
15711587
WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
15721588
WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
15731589

1574-
WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR,
1575-
RREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2) & 0x7FFFFFFF);
1590+
/* Unstall DPG */
1591+
WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),
1592+
0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK);
15761593

15771594
SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS,
15781595
UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
@@ -1630,10 +1647,6 @@ static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
16301647
{
16311648
struct amdgpu_device *adev = ring->adev;
16321649

1633-
if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
1634-
WREG32_SOC15(VCN, ring->me, mmUVD_SCRATCH2,
1635-
lower_32_bits(ring->wptr) | 0x80000000);
1636-
16371650
if (ring->use_doorbell) {
16381651
adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
16391652
WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));

‎drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c‎

Lines changed: 11 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -163,8 +163,17 @@ void rn_update_clocks(struct clk_mgr *clk_mgr_base,
163163
new_clocks->dppclk_khz = 100000;
164164
}
165165

166-
if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
167-
if (clk_mgr->base.clks.dppclk_khz > new_clocks->dppclk_khz)
166+
/*
167+
* Temporally ignore thew 0 cases for disp and dpp clks.
168+
* We may have a new feature that requires 0 clks in the future.
169+
*/
170+
if (new_clocks->dppclk_khz == 0 || new_clocks->dispclk_khz == 0) {
171+
new_clocks->dppclk_khz = clk_mgr_base->clks.dppclk_khz;
172+
new_clocks->dispclk_khz = clk_mgr_base->clks.dispclk_khz;
173+
}
174+
175+
if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) {
176+
if (clk_mgr_base->clks.dppclk_khz > new_clocks->dppclk_khz)
168177
dpp_clock_lowered = true;
169178
clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
170179
update_dppclk = true;

‎drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c‎

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1164,7 +1164,12 @@ int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
11641164
if (ret)
11651165
return ret;
11661166

1167-
crystal_clock_freq = amdgpu_asic_get_xclk(adev);
1167+
/*
1168+
* crystal_clock_freq div by 4 is required since the fan control
1169+
* module refers to 25MHz
1170+
*/
1171+
1172+
crystal_clock_freq = amdgpu_asic_get_xclk(adev) / 4;
11681173
tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
11691174
WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
11701175
REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),

‎drivers/gpu/drm/i915/display/intel_display.c‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -18021,16 +18021,6 @@ int intel_modeset_init_nogem(struct drm_i915_private *i915)
1802118021
if (!HAS_GMCH(i915))
1802218022
sanitize_watermarks(i915);
1802318023

18024-
/*
18025-
* Force all active planes to recompute their states. So that on
18026-
* mode_setcrtc after probe, all the intel_plane_state variables
18027-
* are already calculated and there is no assert_plane warnings
18028-
* during bootup.
18029-
*/
18030-
ret = intel_initial_commit(dev);
18031-
if (ret)
18032-
drm_dbg_kms(&i915->drm, "Initial commit in probe failed.\n");
18033-
1803418024
return 0;
1803518025
}
1803618026

@@ -18039,11 +18029,21 @@ int intel_modeset_init(struct drm_i915_private *i915)
1803918029
{
1804018030
int ret;
1804118031

18042-
intel_overlay_setup(i915);
18043-
1804418032
if (!HAS_DISPLAY(i915))
1804518033
return 0;
1804618034

18035+
/*
18036+
* Force all active planes to recompute their states. So that on
18037+
* mode_setcrtc after probe, all the intel_plane_state variables
18038+
* are already calculated and there is no assert_plane warnings
18039+
* during bootup.
18040+
*/
18041+
ret = intel_initial_commit(&i915->drm);
18042+
if (ret)
18043+
return ret;
18044+
18045+
intel_overlay_setup(i915);
18046+
1804718047
ret = intel_fbdev_init(&i915->drm);
1804818048
if (ret)
1804918049
return ret;

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