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Merge tag 'drm-fixes-2020-11-06-1' of git://anongit.freedesktop.org/drm/drm
Pull drm fixes from Dave Airlie: "It's Friday here so that means another installment of drm fixes to distract you from the counting process. Changes all over the place, the amdgpu changes contain support for a new GPU that is close to current one already in the tree (Green Sardine) so it shouldn't have much side effects. Otherwise imx has a few cleanup patches and fixes, amdgpu and i915 have around the usual smattering of fixes, fonts got constified, and vc4/panfrost has some minor fixes. All in all a fairly regular rc3. We have an outstanding nouveau regression, but the author is looking into the fix, so should be here next week. I now return you to counting. fonts: - constify font structures. MAINTAINERS: - Fix path for amdgpu power management amdgpu: - Add support for more navi1x SKUs - Fix for suspend on CI dGPUs - VCN DPG fix for Picasso - Sienna Cichlid fixes - Polaris DPM fix - Add support for Green Sardine amdkfd: - Fix an allocation failure check i915: - Fix set domain's cache coherency - Fixes around breadcrumbs - Fix encoder lookup during PSR atomic - Hold onto an explicit ref to i915_vma_work.pinned - gvt: HWSP reset handling fix - gvt: flush workaround - gvt: vGPU context pin/unpin - gvt: mmio cmd access fix for bxt/apl imx: - drop unused functions and callbacks - reuse imx_drm_encoder_parse_of - spinlock rework - memory leak fix - minor cleanups vc4: - resource cleanup fix panfrost: - madvise/shrinker fix" * tag 'drm-fixes-2020-11-06-1' of git://anongit.freedesktop.org/drm/drm: (55 commits) drm/amdgpu/display: remove DRM_AMD_DC_GREEN_SARDINE drm/amd/display: Add green_sardine support to DM drm/amd/display: Add green_sardine support to DC drm/amdgpu: enable vcn support for green_sardine (v2) drm/amdgpu: enable green_sardine_asd.bin loading (v2) drm/amdgpu/sdma: add sdma engine support for green_sardine (v2) drm/amdgpu: add gfx support for green_sardine (v2) drm/amdgpu: add soc15 common ip block support for green_sardine (v3) drm/amdgpu: add green_sardine support for gpu_info and ip block setting (v2) drm/amdgpu: add Green_Sardine APU flag drm/amdgpu: resolved ASD loading issue on sienna amdkfd: Check kvmalloc return before memcpy drm/amdgpu: update golden setting for sienna_cichlid amd/amdgpu: Disable VCN DPG mode for Picasso drm/amdgpu/swsmu: remove duplicate call to smu_set_default_dpm_table drm/i915: Hold onto an explicit ref to i915_vma_work.pinned drm/i915/gt: Flush xcs before tgl breadcrumbs drm/i915/gt: Expose more parameters for emitting writes into the ring drm/i915: Fix encoder lookup during PSR atomic check drm/i915/gt: Use the local HWSP offset during submission ...
2 parents 28ced76 + 356583b commit fc7b66e

65 files changed

Lines changed: 439 additions & 370 deletions

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‎MAINTAINERS‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -934,7 +934,7 @@ M: Evan Quan <evan.quan@amd.com>
934934
L: amd-gfx@lists.freedesktop.org
935935
S: Supported
936936
T: git git://people.freedesktop.org/~agd5f/linux
937-
F: drivers/gpu/drm/amd/powerplay/
937+
F: drivers/gpu/drm/amd/pm/powerplay/
938938

939939
AMD SEATTLE DEVICE TREE SUPPORT
940940
M: Brijesh Singh <brijeshkumar.singh@amd.com>

‎drivers/gpu/drm/amd/amdgpu/amdgpu_device.c‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -80,6 +80,7 @@ MODULE_FIRMWARE("amdgpu/renoir_gpu_info.bin");
8080
MODULE_FIRMWARE("amdgpu/navi10_gpu_info.bin");
8181
MODULE_FIRMWARE("amdgpu/navi14_gpu_info.bin");
8282
MODULE_FIRMWARE("amdgpu/navi12_gpu_info.bin");
83+
MODULE_FIRMWARE("amdgpu/green_sardine_gpu_info.bin");
8384

8485
#define AMDGPU_RESUME_MS 2000
8586

@@ -1805,7 +1806,10 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev)
18051806
chip_name = "arcturus";
18061807
break;
18071808
case CHIP_RENOIR:
1808-
chip_name = "renoir";
1809+
if (adev->apu_flags & AMD_APU_IS_RENOIR)
1810+
chip_name = "renoir";
1811+
else
1812+
chip_name = "green_sardine";
18091813
break;
18101814
case CHIP_NAVI10:
18111815
chip_name = "navi10";

‎drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2524,6 +2524,7 @@ int parse_ta_bin_descriptor(struct psp_context *psp,
25242524
psp->asd_feature_version = le32_to_cpu(desc->fw_version);
25252525
psp->asd_ucode_size = le32_to_cpu(desc->size_bytes);
25262526
psp->asd_start_addr = ucode_start_addr;
2527+
psp->asd_fw = psp->ta_fw;
25272528
break;
25282529
case TA_FW_TYPE_PSP_XGMI:
25292530
psp->ta_xgmi_ucode_version = le32_to_cpu(desc->fw_version);

‎drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c‎

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -39,6 +39,7 @@
3939
#define FIRMWARE_RAVEN2 "amdgpu/raven2_vcn.bin"
4040
#define FIRMWARE_ARCTURUS "amdgpu/arcturus_vcn.bin"
4141
#define FIRMWARE_RENOIR "amdgpu/renoir_vcn.bin"
42+
#define FIRMWARE_GREEN_SARDINE "amdgpu/green_sardine_vcn.bin"
4243
#define FIRMWARE_NAVI10 "amdgpu/navi10_vcn.bin"
4344
#define FIRMWARE_NAVI14 "amdgpu/navi14_vcn.bin"
4445
#define FIRMWARE_NAVI12 "amdgpu/navi12_vcn.bin"
@@ -50,6 +51,7 @@ MODULE_FIRMWARE(FIRMWARE_PICASSO);
5051
MODULE_FIRMWARE(FIRMWARE_RAVEN2);
5152
MODULE_FIRMWARE(FIRMWARE_ARCTURUS);
5253
MODULE_FIRMWARE(FIRMWARE_RENOIR);
54+
MODULE_FIRMWARE(FIRMWARE_GREEN_SARDINE);
5355
MODULE_FIRMWARE(FIRMWARE_NAVI10);
5456
MODULE_FIRMWARE(FIRMWARE_NAVI14);
5557
MODULE_FIRMWARE(FIRMWARE_NAVI12);
@@ -89,7 +91,11 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
8991
adev->vcn.indirect_sram = true;
9092
break;
9193
case CHIP_RENOIR:
92-
fw_name = FIRMWARE_RENOIR;
94+
if (adev->apu_flags & AMD_APU_IS_RENOIR)
95+
fw_name = FIRMWARE_RENOIR;
96+
else
97+
fw_name = FIRMWARE_GREEN_SARDINE;
98+
9399
if ((adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) &&
94100
(adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG))
95101
adev->vcn.indirect_sram = true;

‎drivers/gpu/drm/amd/amdgpu/cik.c‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1336,11 +1336,13 @@ cik_asic_reset_method(struct amdgpu_device *adev)
13361336

13371337
switch (adev->asic_type) {
13381338
case CHIP_BONAIRE:
1339-
case CHIP_HAWAII:
13401339
/* disable baco reset until it works */
13411340
/* smu7_asic_get_baco_capability(adev, &baco_reset); */
13421341
baco_reset = false;
13431342
break;
1343+
case CHIP_HAWAII:
1344+
baco_reset = cik_asic_supports_baco(adev);
1345+
break;
13441346
default:
13451347
baco_reset = false;
13461348
break;

‎drivers/gpu/drm/amd/amdgpu/cik_sdma.c‎

Lines changed: 12 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -1071,22 +1071,19 @@ static int cik_sdma_soft_reset(void *handle)
10711071
{
10721072
u32 srbm_soft_reset = 0;
10731073
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1074-
u32 tmp = RREG32(mmSRBM_STATUS2);
1074+
u32 tmp;
10751075

1076-
if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
1077-
/* sdma0 */
1078-
tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1079-
tmp |= SDMA0_F32_CNTL__HALT_MASK;
1080-
WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1081-
srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1082-
}
1083-
if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
1084-
/* sdma1 */
1085-
tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1086-
tmp |= SDMA0_F32_CNTL__HALT_MASK;
1087-
WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1088-
srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1089-
}
1076+
/* sdma0 */
1077+
tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1078+
tmp |= SDMA0_F32_CNTL__HALT_MASK;
1079+
WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1080+
srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1081+
1082+
/* sdma1 */
1083+
tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1084+
tmp |= SDMA0_F32_CNTL__HALT_MASK;
1085+
WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
1086+
srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
10901087

10911088
if (srbm_soft_reset) {
10921089
tmp = RREG32(mmSRBM_SOFT_RESET);

‎drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -128,6 +128,9 @@
128128
#define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3
129129
#define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK 0x00000008L
130130

131+
#define mmCGTT_SPI_CS_CLK_CTRL 0x507c
132+
#define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX 1
133+
131134
MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
132135
MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
133136
MODULE_FIRMWARE("amdgpu/navi10_me.bin");
@@ -3094,6 +3097,7 @@ static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] =
30943097

30953098
static const struct soc15_reg_golden golden_settings_gc_10_3[] =
30963099
{
3100+
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
30973101
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
30983102
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
30993103
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),

‎drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c‎

Lines changed: 11 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -117,6 +117,13 @@ MODULE_FIRMWARE("amdgpu/renoir_mec.bin");
117117
MODULE_FIRMWARE("amdgpu/renoir_mec2.bin");
118118
MODULE_FIRMWARE("amdgpu/renoir_rlc.bin");
119119

120+
MODULE_FIRMWARE("amdgpu/green_sardine_ce.bin");
121+
MODULE_FIRMWARE("amdgpu/green_sardine_pfp.bin");
122+
MODULE_FIRMWARE("amdgpu/green_sardine_me.bin");
123+
MODULE_FIRMWARE("amdgpu/green_sardine_mec.bin");
124+
MODULE_FIRMWARE("amdgpu/green_sardine_mec2.bin");
125+
MODULE_FIRMWARE("amdgpu/green_sardine_rlc.bin");
126+
120127
#define mmTCP_CHAN_STEER_0_ARCT 0x0b03
121128
#define mmTCP_CHAN_STEER_0_ARCT_BASE_IDX 0
122129
#define mmTCP_CHAN_STEER_1_ARCT 0x0b04
@@ -1630,7 +1637,10 @@ static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
16301637
chip_name = "arcturus";
16311638
break;
16321639
case CHIP_RENOIR:
1633-
chip_name = "renoir";
1640+
if (adev->apu_flags & AMD_APU_IS_RENOIR)
1641+
chip_name = "renoir";
1642+
else
1643+
chip_name = "green_sardine";
16341644
break;
16351645
default:
16361646
BUG();

‎drivers/gpu/drm/amd/amdgpu/nv.c‎

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -455,10 +455,11 @@ void nv_set_virt_ops(struct amdgpu_device *adev)
455455
adev->virt.ops = &xgpu_nv_virt_ops;
456456
}
457457

458-
static bool nv_is_blockchain_sku(struct pci_dev *pdev)
458+
static bool nv_is_headless_sku(struct pci_dev *pdev)
459459
{
460-
if (pdev->device == 0x731E &&
461-
(pdev->revision == 0xC6 || pdev->revision == 0xC7))
460+
if ((pdev->device == 0x731E &&
461+
(pdev->revision == 0xC6 || pdev->revision == 0xC7)) ||
462+
(pdev->device == 0x7340 && pdev->revision == 0xC9))
462463
return true;
463464
return false;
464465
}
@@ -492,15 +493,15 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
492493
amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
493494
#if defined(CONFIG_DRM_AMD_DC)
494495
else if (amdgpu_device_has_dc_support(adev) &&
495-
!nv_is_blockchain_sku(adev->pdev))
496+
!nv_is_headless_sku(adev->pdev))
496497
amdgpu_device_ip_block_add(adev, &dm_ip_block);
497498
#endif
498499
amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
499500
amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block);
500501
if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
501502
!amdgpu_sriov_vf(adev))
502503
amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
503-
if (!nv_is_blockchain_sku(adev->pdev))
504+
if (!nv_is_headless_sku(adev->pdev))
504505
amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
505506
amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
506507
if (adev->enable_mes)

‎drivers/gpu/drm/amd/amdgpu/psp_v12_0.c‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -39,6 +39,7 @@
3939

4040
MODULE_FIRMWARE("amdgpu/renoir_asd.bin");
4141
MODULE_FIRMWARE("amdgpu/renoir_ta.bin");
42+
MODULE_FIRMWARE("amdgpu/green_sardine_asd.bin");
4243

4344
/* address block */
4445
#define smnMP1_FIRMWARE_FLAGS 0x3010024
@@ -54,7 +55,10 @@ static int psp_v12_0_init_microcode(struct psp_context *psp)
5455

5556
switch (adev->asic_type) {
5657
case CHIP_RENOIR:
57-
chip_name = "renoir";
58+
if (adev->apu_flags & AMD_APU_IS_RENOIR)
59+
chip_name = "renoir";
60+
else
61+
chip_name = "green_sardine";
5862
break;
5963
default:
6064
BUG();

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