The remainder of the data structure consists of list entries specifying the individual I/O pins of the card in order of how they will be allocated by the firmware. For instance the first six pins are used to provision two encoders with a,b and index connections: `[S.ENCB,1],[S.ENCA,1],[S.ENCB,0],[S.ENCA,0],[S.ENCI,1],[S.ENCI,0]`. The next two pins are two pwmgens: `[S.PWMP,1],[S.PWMP,0]`. The order of these pins is not arbitrary, and must match what the specific firmware on the card is expecting. This information is supplied from Mesa in the form of pin files, typically shipped with the firmware files. In our case there are 48 entries because there are 48 I/O pins.
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