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2172 lines (1941 loc) · 141 KB
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# SPDX-FileCopyrightText: Copyright (c) 2025-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
#
# SPDX-License-Identifier: LicenseRef-NVIDIA-SOFTWARE-LICENSE
#
# This code was automatically generated across versions from 12.9.1 to 13.2.0, generator version 0.3.1.dev1422+gf4812259e.d20260318. Do not modify it directly.
from libc.stdint cimport int64_t
###############################################################################
# Types (structs, enums, ...)
###############################################################################
# enums
ctypedef enum nvmlBridgeChipType_t "nvmlBridgeChipType_t":
NVML_BRIDGE_CHIP_PLX "NVML_BRIDGE_CHIP_PLX" = 0
NVML_BRIDGE_CHIP_BRO4 "NVML_BRIDGE_CHIP_BRO4" = 1
ctypedef enum nvmlNvLinkUtilizationCountUnits_t "nvmlNvLinkUtilizationCountUnits_t":
NVML_NVLINK_COUNTER_UNIT_CYCLES "NVML_NVLINK_COUNTER_UNIT_CYCLES" = 0
NVML_NVLINK_COUNTER_UNIT_PACKETS "NVML_NVLINK_COUNTER_UNIT_PACKETS" = 1
NVML_NVLINK_COUNTER_UNIT_BYTES "NVML_NVLINK_COUNTER_UNIT_BYTES" = 2
NVML_NVLINK_COUNTER_UNIT_RESERVED "NVML_NVLINK_COUNTER_UNIT_RESERVED" = 3
NVML_NVLINK_COUNTER_UNIT_COUNT "NVML_NVLINK_COUNTER_UNIT_COUNT"
ctypedef enum nvmlNvLinkUtilizationCountPktTypes_t "nvmlNvLinkUtilizationCountPktTypes_t":
NVML_NVLINK_COUNTER_PKTFILTER_NOP "NVML_NVLINK_COUNTER_PKTFILTER_NOP" = 0x1
NVML_NVLINK_COUNTER_PKTFILTER_READ "NVML_NVLINK_COUNTER_PKTFILTER_READ" = 0x2
NVML_NVLINK_COUNTER_PKTFILTER_WRITE "NVML_NVLINK_COUNTER_PKTFILTER_WRITE" = 0x4
NVML_NVLINK_COUNTER_PKTFILTER_RATOM "NVML_NVLINK_COUNTER_PKTFILTER_RATOM" = 0x8
NVML_NVLINK_COUNTER_PKTFILTER_NRATOM "NVML_NVLINK_COUNTER_PKTFILTER_NRATOM" = 0x10
NVML_NVLINK_COUNTER_PKTFILTER_FLUSH "NVML_NVLINK_COUNTER_PKTFILTER_FLUSH" = 0x20
NVML_NVLINK_COUNTER_PKTFILTER_RESPDATA "NVML_NVLINK_COUNTER_PKTFILTER_RESPDATA" = 0x40
NVML_NVLINK_COUNTER_PKTFILTER_RESPNODATA "NVML_NVLINK_COUNTER_PKTFILTER_RESPNODATA" = 0x80
NVML_NVLINK_COUNTER_PKTFILTER_ALL "NVML_NVLINK_COUNTER_PKTFILTER_ALL" = 0xFF
ctypedef enum nvmlNvLinkCapability_t "nvmlNvLinkCapability_t":
NVML_NVLINK_CAP_P2P_SUPPORTED "NVML_NVLINK_CAP_P2P_SUPPORTED" = 0
NVML_NVLINK_CAP_SYSMEM_ACCESS "NVML_NVLINK_CAP_SYSMEM_ACCESS" = 1
NVML_NVLINK_CAP_P2P_ATOMICS "NVML_NVLINK_CAP_P2P_ATOMICS" = 2
NVML_NVLINK_CAP_SYSMEM_ATOMICS "NVML_NVLINK_CAP_SYSMEM_ATOMICS" = 3
NVML_NVLINK_CAP_SLI_BRIDGE "NVML_NVLINK_CAP_SLI_BRIDGE" = 4
NVML_NVLINK_CAP_VALID "NVML_NVLINK_CAP_VALID" = 5
NVML_NVLINK_CAP_COUNT "NVML_NVLINK_CAP_COUNT"
ctypedef enum nvmlNvLinkErrorCounter_t "nvmlNvLinkErrorCounter_t":
NVML_NVLINK_ERROR_DL_REPLAY "NVML_NVLINK_ERROR_DL_REPLAY" = 0
NVML_NVLINK_ERROR_DL_RECOVERY "NVML_NVLINK_ERROR_DL_RECOVERY" = 1
NVML_NVLINK_ERROR_DL_CRC_FLIT "NVML_NVLINK_ERROR_DL_CRC_FLIT" = 2
NVML_NVLINK_ERROR_DL_CRC_DATA "NVML_NVLINK_ERROR_DL_CRC_DATA" = 3
NVML_NVLINK_ERROR_DL_ECC_DATA "NVML_NVLINK_ERROR_DL_ECC_DATA" = 4
NVML_NVLINK_ERROR_COUNT "NVML_NVLINK_ERROR_COUNT"
ctypedef enum nvmlIntNvLinkDeviceType_t "nvmlIntNvLinkDeviceType_t":
NVML_NVLINK_DEVICE_TYPE_GPU "NVML_NVLINK_DEVICE_TYPE_GPU" = 0x00
NVML_NVLINK_DEVICE_TYPE_IBMNPU "NVML_NVLINK_DEVICE_TYPE_IBMNPU" = 0x01
NVML_NVLINK_DEVICE_TYPE_SWITCH "NVML_NVLINK_DEVICE_TYPE_SWITCH" = 0x02
NVML_NVLINK_DEVICE_TYPE_UNKNOWN "NVML_NVLINK_DEVICE_TYPE_UNKNOWN" = 0xFF
ctypedef enum nvmlGpuTopologyLevel_t "nvmlGpuTopologyLevel_t":
NVML_TOPOLOGY_INTERNAL "NVML_TOPOLOGY_INTERNAL" = 0
NVML_TOPOLOGY_SINGLE "NVML_TOPOLOGY_SINGLE" = 10
NVML_TOPOLOGY_MULTIPLE "NVML_TOPOLOGY_MULTIPLE" = 20
NVML_TOPOLOGY_HOSTBRIDGE "NVML_TOPOLOGY_HOSTBRIDGE" = 30
NVML_TOPOLOGY_NODE "NVML_TOPOLOGY_NODE" = 40
NVML_TOPOLOGY_SYSTEM "NVML_TOPOLOGY_SYSTEM" = 50
ctypedef enum nvmlGpuP2PStatus_t "nvmlGpuP2PStatus_t":
NVML_P2P_STATUS_OK "NVML_P2P_STATUS_OK" = 0
NVML_P2P_STATUS_CHIPSET_NOT_SUPPORED "NVML_P2P_STATUS_CHIPSET_NOT_SUPPORED"
NVML_P2P_STATUS_CHIPSET_NOT_SUPPORTED "NVML_P2P_STATUS_CHIPSET_NOT_SUPPORTED" = NVML_P2P_STATUS_CHIPSET_NOT_SUPPORED
NVML_P2P_STATUS_GPU_NOT_SUPPORTED "NVML_P2P_STATUS_GPU_NOT_SUPPORTED"
NVML_P2P_STATUS_IOH_TOPOLOGY_NOT_SUPPORTED "NVML_P2P_STATUS_IOH_TOPOLOGY_NOT_SUPPORTED"
NVML_P2P_STATUS_DISABLED_BY_REGKEY "NVML_P2P_STATUS_DISABLED_BY_REGKEY"
NVML_P2P_STATUS_NOT_SUPPORTED "NVML_P2P_STATUS_NOT_SUPPORTED"
NVML_P2P_STATUS_UNKNOWN "NVML_P2P_STATUS_UNKNOWN"
ctypedef enum nvmlGpuP2PCapsIndex_t "nvmlGpuP2PCapsIndex_t":
NVML_P2P_CAPS_INDEX_READ "NVML_P2P_CAPS_INDEX_READ" = 0
NVML_P2P_CAPS_INDEX_WRITE "NVML_P2P_CAPS_INDEX_WRITE" = 1
NVML_P2P_CAPS_INDEX_NVLINK "NVML_P2P_CAPS_INDEX_NVLINK" = 2
NVML_P2P_CAPS_INDEX_ATOMICS "NVML_P2P_CAPS_INDEX_ATOMICS" = 3
NVML_P2P_CAPS_INDEX_PCI "NVML_P2P_CAPS_INDEX_PCI" = 4
NVML_P2P_CAPS_INDEX_PROP "NVML_P2P_CAPS_INDEX_PROP" = NVML_P2P_CAPS_INDEX_PCI
NVML_P2P_CAPS_INDEX_UNKNOWN "NVML_P2P_CAPS_INDEX_UNKNOWN" = 5
ctypedef enum nvmlSamplingType_t "nvmlSamplingType_t":
NVML_TOTAL_POWER_SAMPLES "NVML_TOTAL_POWER_SAMPLES" = 0
NVML_GPU_UTILIZATION_SAMPLES "NVML_GPU_UTILIZATION_SAMPLES" = 1
NVML_MEMORY_UTILIZATION_SAMPLES "NVML_MEMORY_UTILIZATION_SAMPLES" = 2
NVML_ENC_UTILIZATION_SAMPLES "NVML_ENC_UTILIZATION_SAMPLES" = 3
NVML_DEC_UTILIZATION_SAMPLES "NVML_DEC_UTILIZATION_SAMPLES" = 4
NVML_PROCESSOR_CLK_SAMPLES "NVML_PROCESSOR_CLK_SAMPLES" = 5
NVML_MEMORY_CLK_SAMPLES "NVML_MEMORY_CLK_SAMPLES" = 6
NVML_MODULE_POWER_SAMPLES "NVML_MODULE_POWER_SAMPLES" = 7
NVML_JPG_UTILIZATION_SAMPLES "NVML_JPG_UTILIZATION_SAMPLES" = 8
NVML_OFA_UTILIZATION_SAMPLES "NVML_OFA_UTILIZATION_SAMPLES" = 9
NVML_SAMPLINGTYPE_COUNT "NVML_SAMPLINGTYPE_COUNT"
ctypedef enum nvmlPcieUtilCounter_t "nvmlPcieUtilCounter_t":
NVML_PCIE_UTIL_TX_BYTES "NVML_PCIE_UTIL_TX_BYTES" = 0
NVML_PCIE_UTIL_RX_BYTES "NVML_PCIE_UTIL_RX_BYTES" = 1
NVML_PCIE_UTIL_COUNT "NVML_PCIE_UTIL_COUNT"
ctypedef enum nvmlValueType_t "nvmlValueType_t":
NVML_VALUE_TYPE_DOUBLE "NVML_VALUE_TYPE_DOUBLE" = 0
NVML_VALUE_TYPE_UNSIGNED_INT "NVML_VALUE_TYPE_UNSIGNED_INT" = 1
NVML_VALUE_TYPE_UNSIGNED_LONG "NVML_VALUE_TYPE_UNSIGNED_LONG" = 2
NVML_VALUE_TYPE_UNSIGNED_LONG_LONG "NVML_VALUE_TYPE_UNSIGNED_LONG_LONG" = 3
NVML_VALUE_TYPE_SIGNED_LONG_LONG "NVML_VALUE_TYPE_SIGNED_LONG_LONG" = 4
NVML_VALUE_TYPE_SIGNED_INT "NVML_VALUE_TYPE_SIGNED_INT" = 5
NVML_VALUE_TYPE_UNSIGNED_SHORT "NVML_VALUE_TYPE_UNSIGNED_SHORT" = 6
NVML_VALUE_TYPE_COUNT "NVML_VALUE_TYPE_COUNT"
ctypedef enum nvmlPerfPolicyType_t "nvmlPerfPolicyType_t":
NVML_PERF_POLICY_POWER "NVML_PERF_POLICY_POWER" = 0
NVML_PERF_POLICY_THERMAL "NVML_PERF_POLICY_THERMAL" = 1
NVML_PERF_POLICY_SYNC_BOOST "NVML_PERF_POLICY_SYNC_BOOST" = 2
NVML_PERF_POLICY_BOARD_LIMIT "NVML_PERF_POLICY_BOARD_LIMIT" = 3
NVML_PERF_POLICY_LOW_UTILIZATION "NVML_PERF_POLICY_LOW_UTILIZATION" = 4
NVML_PERF_POLICY_RELIABILITY "NVML_PERF_POLICY_RELIABILITY" = 5
NVML_PERF_POLICY_TOTAL_APP_CLOCKS "NVML_PERF_POLICY_TOTAL_APP_CLOCKS" = 10
NVML_PERF_POLICY_TOTAL_BASE_CLOCKS "NVML_PERF_POLICY_TOTAL_BASE_CLOCKS" = 11
NVML_PERF_POLICY_COUNT "NVML_PERF_POLICY_COUNT"
ctypedef enum nvmlThermalTarget_t "nvmlThermalTarget_t":
NVML_THERMAL_TARGET_NONE "NVML_THERMAL_TARGET_NONE" = 0
NVML_THERMAL_TARGET_GPU "NVML_THERMAL_TARGET_GPU" = 1
NVML_THERMAL_TARGET_MEMORY "NVML_THERMAL_TARGET_MEMORY" = 2
NVML_THERMAL_TARGET_POWER_SUPPLY "NVML_THERMAL_TARGET_POWER_SUPPLY" = 4
NVML_THERMAL_TARGET_BOARD "NVML_THERMAL_TARGET_BOARD" = 8
NVML_THERMAL_TARGET_VCD_BOARD "NVML_THERMAL_TARGET_VCD_BOARD" = 9
NVML_THERMAL_TARGET_VCD_INLET "NVML_THERMAL_TARGET_VCD_INLET" = 10
NVML_THERMAL_TARGET_VCD_OUTLET "NVML_THERMAL_TARGET_VCD_OUTLET" = 11
NVML_THERMAL_TARGET_ALL "NVML_THERMAL_TARGET_ALL" = 15
NVML_THERMAL_TARGET_UNKNOWN "NVML_THERMAL_TARGET_UNKNOWN" = -(1)
ctypedef enum nvmlThermalController_t "nvmlThermalController_t":
NVML_THERMAL_CONTROLLER_NONE "NVML_THERMAL_CONTROLLER_NONE" = 0
NVML_THERMAL_CONTROLLER_GPU_INTERNAL "NVML_THERMAL_CONTROLLER_GPU_INTERNAL"
NVML_THERMAL_CONTROLLER_ADM1032 "NVML_THERMAL_CONTROLLER_ADM1032"
NVML_THERMAL_CONTROLLER_ADT7461 "NVML_THERMAL_CONTROLLER_ADT7461"
NVML_THERMAL_CONTROLLER_MAX6649 "NVML_THERMAL_CONTROLLER_MAX6649"
NVML_THERMAL_CONTROLLER_MAX1617 "NVML_THERMAL_CONTROLLER_MAX1617"
NVML_THERMAL_CONTROLLER_LM99 "NVML_THERMAL_CONTROLLER_LM99"
NVML_THERMAL_CONTROLLER_LM89 "NVML_THERMAL_CONTROLLER_LM89"
NVML_THERMAL_CONTROLLER_LM64 "NVML_THERMAL_CONTROLLER_LM64"
NVML_THERMAL_CONTROLLER_G781 "NVML_THERMAL_CONTROLLER_G781"
NVML_THERMAL_CONTROLLER_ADT7473 "NVML_THERMAL_CONTROLLER_ADT7473"
NVML_THERMAL_CONTROLLER_SBMAX6649 "NVML_THERMAL_CONTROLLER_SBMAX6649"
NVML_THERMAL_CONTROLLER_VBIOSEVT "NVML_THERMAL_CONTROLLER_VBIOSEVT"
NVML_THERMAL_CONTROLLER_OS "NVML_THERMAL_CONTROLLER_OS"
NVML_THERMAL_CONTROLLER_NVSYSCON_CANOAS "NVML_THERMAL_CONTROLLER_NVSYSCON_CANOAS"
NVML_THERMAL_CONTROLLER_NVSYSCON_E551 "NVML_THERMAL_CONTROLLER_NVSYSCON_E551"
NVML_THERMAL_CONTROLLER_MAX6649R "NVML_THERMAL_CONTROLLER_MAX6649R"
NVML_THERMAL_CONTROLLER_ADT7473S "NVML_THERMAL_CONTROLLER_ADT7473S"
NVML_THERMAL_CONTROLLER_UNKNOWN "NVML_THERMAL_CONTROLLER_UNKNOWN" = -(1)
ctypedef enum nvmlCoolerControl_t "nvmlCoolerControl_t":
NVML_THERMAL_COOLER_SIGNAL_NONE "NVML_THERMAL_COOLER_SIGNAL_NONE" = 0
NVML_THERMAL_COOLER_SIGNAL_TOGGLE "NVML_THERMAL_COOLER_SIGNAL_TOGGLE" = 1
NVML_THERMAL_COOLER_SIGNAL_VARIABLE "NVML_THERMAL_COOLER_SIGNAL_VARIABLE" = 2
NVML_THERMAL_COOLER_SIGNAL_COUNT "NVML_THERMAL_COOLER_SIGNAL_COUNT"
ctypedef enum nvmlCoolerTarget_t "nvmlCoolerTarget_t":
NVML_THERMAL_COOLER_TARGET_NONE "NVML_THERMAL_COOLER_TARGET_NONE" = (1 << 0)
NVML_THERMAL_COOLER_TARGET_GPU "NVML_THERMAL_COOLER_TARGET_GPU" = (1 << 1)
NVML_THERMAL_COOLER_TARGET_MEMORY "NVML_THERMAL_COOLER_TARGET_MEMORY" = (1 << 2)
NVML_THERMAL_COOLER_TARGET_POWER_SUPPLY "NVML_THERMAL_COOLER_TARGET_POWER_SUPPLY" = (1 << 3)
NVML_THERMAL_COOLER_TARGET_GPU_RELATED "NVML_THERMAL_COOLER_TARGET_GPU_RELATED" = ((NVML_THERMAL_COOLER_TARGET_GPU | NVML_THERMAL_COOLER_TARGET_MEMORY) | NVML_THERMAL_COOLER_TARGET_POWER_SUPPLY)
ctypedef enum nvmlUUIDType_t "nvmlUUIDType_t":
NVML_UUID_TYPE_NONE "NVML_UUID_TYPE_NONE" = 0
NVML_UUID_TYPE_ASCII "NVML_UUID_TYPE_ASCII" = 1
NVML_UUID_TYPE_BINARY "NVML_UUID_TYPE_BINARY" = 2
ctypedef enum nvmlEnableState_t "nvmlEnableState_t":
NVML_FEATURE_DISABLED "NVML_FEATURE_DISABLED" = 0
NVML_FEATURE_ENABLED "NVML_FEATURE_ENABLED" = 1
ctypedef enum nvmlBrandType_t "nvmlBrandType_t":
NVML_BRAND_UNKNOWN "NVML_BRAND_UNKNOWN" = 0
NVML_BRAND_QUADRO "NVML_BRAND_QUADRO" = 1
NVML_BRAND_TESLA "NVML_BRAND_TESLA" = 2
NVML_BRAND_NVS "NVML_BRAND_NVS" = 3
NVML_BRAND_GRID "NVML_BRAND_GRID" = 4
NVML_BRAND_GEFORCE "NVML_BRAND_GEFORCE" = 5
NVML_BRAND_TITAN "NVML_BRAND_TITAN" = 6
NVML_BRAND_NVIDIA_VAPPS "NVML_BRAND_NVIDIA_VAPPS" = 7
NVML_BRAND_NVIDIA_VPC "NVML_BRAND_NVIDIA_VPC" = 8
NVML_BRAND_NVIDIA_VCS "NVML_BRAND_NVIDIA_VCS" = 9
NVML_BRAND_NVIDIA_VWS "NVML_BRAND_NVIDIA_VWS" = 10
NVML_BRAND_NVIDIA_CLOUD_GAMING "NVML_BRAND_NVIDIA_CLOUD_GAMING" = 11
NVML_BRAND_NVIDIA_VGAMING "NVML_BRAND_NVIDIA_VGAMING" = NVML_BRAND_NVIDIA_CLOUD_GAMING
NVML_BRAND_QUADRO_RTX "NVML_BRAND_QUADRO_RTX" = 12
NVML_BRAND_NVIDIA_RTX "NVML_BRAND_NVIDIA_RTX" = 13
NVML_BRAND_NVIDIA "NVML_BRAND_NVIDIA" = 14
NVML_BRAND_GEFORCE_RTX "NVML_BRAND_GEFORCE_RTX" = 15
NVML_BRAND_TITAN_RTX "NVML_BRAND_TITAN_RTX" = 16
NVML_BRAND_COUNT "NVML_BRAND_COUNT" = 18
ctypedef enum nvmlTemperatureThresholds_t "nvmlTemperatureThresholds_t":
NVML_TEMPERATURE_THRESHOLD_SHUTDOWN "NVML_TEMPERATURE_THRESHOLD_SHUTDOWN" = 0
NVML_TEMPERATURE_THRESHOLD_SLOWDOWN "NVML_TEMPERATURE_THRESHOLD_SLOWDOWN" = 1
NVML_TEMPERATURE_THRESHOLD_MEM_MAX "NVML_TEMPERATURE_THRESHOLD_MEM_MAX" = 2
NVML_TEMPERATURE_THRESHOLD_GPU_MAX "NVML_TEMPERATURE_THRESHOLD_GPU_MAX" = 3
NVML_TEMPERATURE_THRESHOLD_ACOUSTIC_MIN "NVML_TEMPERATURE_THRESHOLD_ACOUSTIC_MIN" = 4
NVML_TEMPERATURE_THRESHOLD_ACOUSTIC_CURR "NVML_TEMPERATURE_THRESHOLD_ACOUSTIC_CURR" = 5
NVML_TEMPERATURE_THRESHOLD_ACOUSTIC_MAX "NVML_TEMPERATURE_THRESHOLD_ACOUSTIC_MAX" = 6
NVML_TEMPERATURE_THRESHOLD_GPS_CURR "NVML_TEMPERATURE_THRESHOLD_GPS_CURR" = 7
NVML_TEMPERATURE_THRESHOLD_COUNT "NVML_TEMPERATURE_THRESHOLD_COUNT"
ctypedef enum nvmlTemperatureSensors_t "nvmlTemperatureSensors_t":
NVML_TEMPERATURE_GPU "NVML_TEMPERATURE_GPU" = 0
NVML_TEMPERATURE_COUNT "NVML_TEMPERATURE_COUNT"
ctypedef enum nvmlComputeMode_t "nvmlComputeMode_t":
NVML_COMPUTEMODE_DEFAULT "NVML_COMPUTEMODE_DEFAULT" = 0
NVML_COMPUTEMODE_EXCLUSIVE_THREAD "NVML_COMPUTEMODE_EXCLUSIVE_THREAD" = 1
NVML_COMPUTEMODE_PROHIBITED "NVML_COMPUTEMODE_PROHIBITED" = 2
NVML_COMPUTEMODE_EXCLUSIVE_PROCESS "NVML_COMPUTEMODE_EXCLUSIVE_PROCESS" = 3
NVML_COMPUTEMODE_COUNT "NVML_COMPUTEMODE_COUNT"
ctypedef enum nvmlMemoryErrorType_t "nvmlMemoryErrorType_t":
NVML_MEMORY_ERROR_TYPE_CORRECTED "NVML_MEMORY_ERROR_TYPE_CORRECTED" = 0
NVML_MEMORY_ERROR_TYPE_UNCORRECTED "NVML_MEMORY_ERROR_TYPE_UNCORRECTED" = 1
NVML_MEMORY_ERROR_TYPE_COUNT "NVML_MEMORY_ERROR_TYPE_COUNT"
ctypedef enum nvmlNvlinkVersion_t "nvmlNvlinkVersion_t":
NVML_NVLINK_VERSION_INVALID "NVML_NVLINK_VERSION_INVALID" = 0
NVML_NVLINK_VERSION_1_0 "NVML_NVLINK_VERSION_1_0" = 1
NVML_NVLINK_VERSION_2_0 "NVML_NVLINK_VERSION_2_0" = 2
NVML_NVLINK_VERSION_2_2 "NVML_NVLINK_VERSION_2_2" = 3
NVML_NVLINK_VERSION_3_0 "NVML_NVLINK_VERSION_3_0" = 4
NVML_NVLINK_VERSION_3_1 "NVML_NVLINK_VERSION_3_1" = 5
NVML_NVLINK_VERSION_4_0 "NVML_NVLINK_VERSION_4_0" = 6
NVML_NVLINK_VERSION_5_0 "NVML_NVLINK_VERSION_5_0" = 7
ctypedef enum nvmlEccCounterType_t "nvmlEccCounterType_t":
NVML_VOLATILE_ECC "NVML_VOLATILE_ECC" = 0
NVML_AGGREGATE_ECC "NVML_AGGREGATE_ECC" = 1
NVML_ECC_COUNTER_TYPE_COUNT "NVML_ECC_COUNTER_TYPE_COUNT"
ctypedef enum nvmlClockType_t "nvmlClockType_t":
NVML_CLOCK_GRAPHICS "NVML_CLOCK_GRAPHICS" = 0
NVML_CLOCK_SM "NVML_CLOCK_SM" = 1
NVML_CLOCK_MEM "NVML_CLOCK_MEM" = 2
NVML_CLOCK_VIDEO "NVML_CLOCK_VIDEO" = 3
NVML_CLOCK_COUNT "NVML_CLOCK_COUNT"
ctypedef enum nvmlClockId_t "nvmlClockId_t":
NVML_CLOCK_ID_CURRENT "NVML_CLOCK_ID_CURRENT" = 0
NVML_CLOCK_ID_APP_CLOCK_TARGET "NVML_CLOCK_ID_APP_CLOCK_TARGET" = 1
NVML_CLOCK_ID_APP_CLOCK_DEFAULT "NVML_CLOCK_ID_APP_CLOCK_DEFAULT" = 2
NVML_CLOCK_ID_CUSTOMER_BOOST_MAX "NVML_CLOCK_ID_CUSTOMER_BOOST_MAX" = 3
NVML_CLOCK_ID_COUNT "NVML_CLOCK_ID_COUNT"
ctypedef enum nvmlDriverModel_t "nvmlDriverModel_t":
NVML_DRIVER_WDDM "NVML_DRIVER_WDDM" = 0
NVML_DRIVER_WDM "NVML_DRIVER_WDM" = 1
NVML_DRIVER_MCDM "NVML_DRIVER_MCDM" = 2
ctypedef enum nvmlPstates_t "nvmlPstates_t":
NVML_PSTATE_0 "NVML_PSTATE_0" = 0
NVML_PSTATE_1 "NVML_PSTATE_1" = 1
NVML_PSTATE_2 "NVML_PSTATE_2" = 2
NVML_PSTATE_3 "NVML_PSTATE_3" = 3
NVML_PSTATE_4 "NVML_PSTATE_4" = 4
NVML_PSTATE_5 "NVML_PSTATE_5" = 5
NVML_PSTATE_6 "NVML_PSTATE_6" = 6
NVML_PSTATE_7 "NVML_PSTATE_7" = 7
NVML_PSTATE_8 "NVML_PSTATE_8" = 8
NVML_PSTATE_9 "NVML_PSTATE_9" = 9
NVML_PSTATE_10 "NVML_PSTATE_10" = 10
NVML_PSTATE_11 "NVML_PSTATE_11" = 11
NVML_PSTATE_12 "NVML_PSTATE_12" = 12
NVML_PSTATE_13 "NVML_PSTATE_13" = 13
NVML_PSTATE_14 "NVML_PSTATE_14" = 14
NVML_PSTATE_15 "NVML_PSTATE_15" = 15
NVML_PSTATE_UNKNOWN "NVML_PSTATE_UNKNOWN" = 32
ctypedef enum nvmlGpuOperationMode_t "nvmlGpuOperationMode_t":
NVML_GOM_ALL_ON "NVML_GOM_ALL_ON" = 0
NVML_GOM_COMPUTE "NVML_GOM_COMPUTE" = 1
NVML_GOM_LOW_DP "NVML_GOM_LOW_DP" = 2
ctypedef enum nvmlInforomObject_t "nvmlInforomObject_t":
NVML_INFOROM_OEM "NVML_INFOROM_OEM" = 0
NVML_INFOROM_ECC "NVML_INFOROM_ECC" = 1
NVML_INFOROM_POWER "NVML_INFOROM_POWER" = 2
NVML_INFOROM_DEN "NVML_INFOROM_DEN" = 3
NVML_INFOROM_COUNT "NVML_INFOROM_COUNT"
ctypedef enum nvmlReturn_t "nvmlReturn_t":
NVML_SUCCESS "NVML_SUCCESS" = 0
NVML_ERROR_UNINITIALIZED "NVML_ERROR_UNINITIALIZED" = 1
NVML_ERROR_INVALID_ARGUMENT "NVML_ERROR_INVALID_ARGUMENT" = 2
NVML_ERROR_NOT_SUPPORTED "NVML_ERROR_NOT_SUPPORTED" = 3
NVML_ERROR_NO_PERMISSION "NVML_ERROR_NO_PERMISSION" = 4
NVML_ERROR_ALREADY_INITIALIZED "NVML_ERROR_ALREADY_INITIALIZED" = 5
NVML_ERROR_NOT_FOUND "NVML_ERROR_NOT_FOUND" = 6
NVML_ERROR_INSUFFICIENT_SIZE "NVML_ERROR_INSUFFICIENT_SIZE" = 7
NVML_ERROR_INSUFFICIENT_POWER "NVML_ERROR_INSUFFICIENT_POWER" = 8
NVML_ERROR_DRIVER_NOT_LOADED "NVML_ERROR_DRIVER_NOT_LOADED" = 9
NVML_ERROR_TIMEOUT "NVML_ERROR_TIMEOUT" = 10
NVML_ERROR_IRQ_ISSUE "NVML_ERROR_IRQ_ISSUE" = 11
NVML_ERROR_LIBRARY_NOT_FOUND "NVML_ERROR_LIBRARY_NOT_FOUND" = 12
NVML_ERROR_FUNCTION_NOT_FOUND "NVML_ERROR_FUNCTION_NOT_FOUND" = 13
NVML_ERROR_CORRUPTED_INFOROM "NVML_ERROR_CORRUPTED_INFOROM" = 14
NVML_ERROR_GPU_IS_LOST "NVML_ERROR_GPU_IS_LOST" = 15
NVML_ERROR_RESET_REQUIRED "NVML_ERROR_RESET_REQUIRED" = 16
NVML_ERROR_OPERATING_SYSTEM "NVML_ERROR_OPERATING_SYSTEM" = 17
NVML_ERROR_LIB_RM_VERSION_MISMATCH "NVML_ERROR_LIB_RM_VERSION_MISMATCH" = 18
NVML_ERROR_IN_USE "NVML_ERROR_IN_USE" = 19
NVML_ERROR_MEMORY "NVML_ERROR_MEMORY" = 20
NVML_ERROR_NO_DATA "NVML_ERROR_NO_DATA" = 21
NVML_ERROR_VGPU_ECC_NOT_SUPPORTED "NVML_ERROR_VGPU_ECC_NOT_SUPPORTED" = 22
NVML_ERROR_INSUFFICIENT_RESOURCES "NVML_ERROR_INSUFFICIENT_RESOURCES" = 23
NVML_ERROR_FREQ_NOT_SUPPORTED "NVML_ERROR_FREQ_NOT_SUPPORTED" = 24
NVML_ERROR_ARGUMENT_VERSION_MISMATCH "NVML_ERROR_ARGUMENT_VERSION_MISMATCH" = 25
NVML_ERROR_DEPRECATED "NVML_ERROR_DEPRECATED" = 26
NVML_ERROR_NOT_READY "NVML_ERROR_NOT_READY" = 27
NVML_ERROR_GPU_NOT_FOUND "NVML_ERROR_GPU_NOT_FOUND" = 28
NVML_ERROR_INVALID_STATE "NVML_ERROR_INVALID_STATE" = 29
NVML_ERROR_RESET_TYPE_NOT_SUPPORTED "NVML_ERROR_RESET_TYPE_NOT_SUPPORTED" = 30
NVML_ERROR_UNKNOWN "NVML_ERROR_UNKNOWN" = 999
_NVMLRETURN_T_INTERNAL_LOADING_ERROR "_NVMLRETURN_T_INTERNAL_LOADING_ERROR" = -42
ctypedef enum nvmlMemoryLocation_t "nvmlMemoryLocation_t":
NVML_MEMORY_LOCATION_L1_CACHE "NVML_MEMORY_LOCATION_L1_CACHE" = 0
NVML_MEMORY_LOCATION_L2_CACHE "NVML_MEMORY_LOCATION_L2_CACHE" = 1
NVML_MEMORY_LOCATION_DRAM "NVML_MEMORY_LOCATION_DRAM" = 2
NVML_MEMORY_LOCATION_DEVICE_MEMORY "NVML_MEMORY_LOCATION_DEVICE_MEMORY" = 2
NVML_MEMORY_LOCATION_REGISTER_FILE "NVML_MEMORY_LOCATION_REGISTER_FILE" = 3
NVML_MEMORY_LOCATION_TEXTURE_MEMORY "NVML_MEMORY_LOCATION_TEXTURE_MEMORY" = 4
NVML_MEMORY_LOCATION_TEXTURE_SHM "NVML_MEMORY_LOCATION_TEXTURE_SHM" = 5
NVML_MEMORY_LOCATION_CBU "NVML_MEMORY_LOCATION_CBU" = 6
NVML_MEMORY_LOCATION_SRAM "NVML_MEMORY_LOCATION_SRAM" = 7
NVML_MEMORY_LOCATION_COUNT "NVML_MEMORY_LOCATION_COUNT"
ctypedef enum nvmlPageRetirementCause_t "nvmlPageRetirementCause_t":
NVML_PAGE_RETIREMENT_CAUSE_MULTIPLE_SINGLE_BIT_ECC_ERRORS "NVML_PAGE_RETIREMENT_CAUSE_MULTIPLE_SINGLE_BIT_ECC_ERRORS" = 0
NVML_PAGE_RETIREMENT_CAUSE_DOUBLE_BIT_ECC_ERROR "NVML_PAGE_RETIREMENT_CAUSE_DOUBLE_BIT_ECC_ERROR" = 1
NVML_PAGE_RETIREMENT_CAUSE_COUNT "NVML_PAGE_RETIREMENT_CAUSE_COUNT"
ctypedef enum nvmlRestrictedAPI_t "nvmlRestrictedAPI_t":
NVML_RESTRICTED_API_SET_APPLICATION_CLOCKS "NVML_RESTRICTED_API_SET_APPLICATION_CLOCKS" = 0
NVML_RESTRICTED_API_SET_AUTO_BOOSTED_CLOCKS "NVML_RESTRICTED_API_SET_AUTO_BOOSTED_CLOCKS" = 1
NVML_RESTRICTED_API_COUNT "NVML_RESTRICTED_API_COUNT"
ctypedef enum nvmlGpuUtilizationDomainId_t "nvmlGpuUtilizationDomainId_t":
NVML_GPU_UTILIZATION_DOMAIN_GPU "NVML_GPU_UTILIZATION_DOMAIN_GPU" = 0
NVML_GPU_UTILIZATION_DOMAIN_FB "NVML_GPU_UTILIZATION_DOMAIN_FB" = 1
NVML_GPU_UTILIZATION_DOMAIN_VID "NVML_GPU_UTILIZATION_DOMAIN_VID" = 2
NVML_GPU_UTILIZATION_DOMAIN_BUS "NVML_GPU_UTILIZATION_DOMAIN_BUS" = 3
ctypedef enum nvmlGpuVirtualizationMode_t "nvmlGpuVirtualizationMode_t":
NVML_GPU_VIRTUALIZATION_MODE_NONE "NVML_GPU_VIRTUALIZATION_MODE_NONE" = 0
NVML_GPU_VIRTUALIZATION_MODE_PASSTHROUGH "NVML_GPU_VIRTUALIZATION_MODE_PASSTHROUGH" = 1
NVML_GPU_VIRTUALIZATION_MODE_VGPU "NVML_GPU_VIRTUALIZATION_MODE_VGPU" = 2
NVML_GPU_VIRTUALIZATION_MODE_HOST_VGPU "NVML_GPU_VIRTUALIZATION_MODE_HOST_VGPU" = 3
NVML_GPU_VIRTUALIZATION_MODE_HOST_VSGA "NVML_GPU_VIRTUALIZATION_MODE_HOST_VSGA" = 4
ctypedef enum nvmlHostVgpuMode_t "nvmlHostVgpuMode_t":
NVML_HOST_VGPU_MODE_NON_SRIOV "NVML_HOST_VGPU_MODE_NON_SRIOV" = 0
NVML_HOST_VGPU_MODE_SRIOV "NVML_HOST_VGPU_MODE_SRIOV" = 1
ctypedef enum nvmlVgpuVmIdType_t "nvmlVgpuVmIdType_t":
NVML_VGPU_VM_ID_DOMAIN_ID "NVML_VGPU_VM_ID_DOMAIN_ID" = 0
NVML_VGPU_VM_ID_UUID "NVML_VGPU_VM_ID_UUID" = 1
ctypedef enum nvmlVgpuGuestInfoState_t "nvmlVgpuGuestInfoState_t":
NVML_VGPU_INSTANCE_GUEST_INFO_STATE_UNINITIALIZED "NVML_VGPU_INSTANCE_GUEST_INFO_STATE_UNINITIALIZED" = 0
NVML_VGPU_INSTANCE_GUEST_INFO_STATE_INITIALIZED "NVML_VGPU_INSTANCE_GUEST_INFO_STATE_INITIALIZED" = 1
ctypedef enum nvmlGridLicenseFeatureCode_t "nvmlGridLicenseFeatureCode_t":
NVML_GRID_LICENSE_FEATURE_CODE_UNKNOWN "NVML_GRID_LICENSE_FEATURE_CODE_UNKNOWN" = 0
NVML_GRID_LICENSE_FEATURE_CODE_VGPU "NVML_GRID_LICENSE_FEATURE_CODE_VGPU" = 1
NVML_GRID_LICENSE_FEATURE_CODE_NVIDIA_RTX "NVML_GRID_LICENSE_FEATURE_CODE_NVIDIA_RTX" = 2
NVML_GRID_LICENSE_FEATURE_CODE_VWORKSTATION "NVML_GRID_LICENSE_FEATURE_CODE_VWORKSTATION" = NVML_GRID_LICENSE_FEATURE_CODE_NVIDIA_RTX
NVML_GRID_LICENSE_FEATURE_CODE_GAMING "NVML_GRID_LICENSE_FEATURE_CODE_GAMING" = 3
NVML_GRID_LICENSE_FEATURE_CODE_COMPUTE "NVML_GRID_LICENSE_FEATURE_CODE_COMPUTE" = 4
ctypedef enum nvmlVgpuCapability_t "nvmlVgpuCapability_t":
NVML_VGPU_CAP_NVLINK_P2P "NVML_VGPU_CAP_NVLINK_P2P" = 0
NVML_VGPU_CAP_GPUDIRECT "NVML_VGPU_CAP_GPUDIRECT" = 1
NVML_VGPU_CAP_MULTI_VGPU_EXCLUSIVE "NVML_VGPU_CAP_MULTI_VGPU_EXCLUSIVE" = 2
NVML_VGPU_CAP_EXCLUSIVE_TYPE "NVML_VGPU_CAP_EXCLUSIVE_TYPE" = 3
NVML_VGPU_CAP_EXCLUSIVE_SIZE "NVML_VGPU_CAP_EXCLUSIVE_SIZE" = 4
NVML_VGPU_CAP_COUNT "NVML_VGPU_CAP_COUNT"
ctypedef enum nvmlVgpuDriverCapability_t "nvmlVgpuDriverCapability_t":
NVML_VGPU_DRIVER_CAP_HETEROGENEOUS_MULTI_VGPU "NVML_VGPU_DRIVER_CAP_HETEROGENEOUS_MULTI_VGPU" = 0
NVML_VGPU_DRIVER_CAP_WARM_UPDATE "NVML_VGPU_DRIVER_CAP_WARM_UPDATE" = 1
NVML_VGPU_DRIVER_CAP_COUNT "NVML_VGPU_DRIVER_CAP_COUNT"
ctypedef enum nvmlDeviceVgpuCapability_t "nvmlDeviceVgpuCapability_t":
NVML_DEVICE_VGPU_CAP_FRACTIONAL_MULTI_VGPU "NVML_DEVICE_VGPU_CAP_FRACTIONAL_MULTI_VGPU" = 0
NVML_DEVICE_VGPU_CAP_HETEROGENEOUS_TIMESLICE_PROFILES "NVML_DEVICE_VGPU_CAP_HETEROGENEOUS_TIMESLICE_PROFILES" = 1
NVML_DEVICE_VGPU_CAP_HETEROGENEOUS_TIMESLICE_SIZES "NVML_DEVICE_VGPU_CAP_HETEROGENEOUS_TIMESLICE_SIZES" = 2
NVML_DEVICE_VGPU_CAP_READ_DEVICE_BUFFER_BW "NVML_DEVICE_VGPU_CAP_READ_DEVICE_BUFFER_BW" = 3
NVML_DEVICE_VGPU_CAP_WRITE_DEVICE_BUFFER_BW "NVML_DEVICE_VGPU_CAP_WRITE_DEVICE_BUFFER_BW" = 4
NVML_DEVICE_VGPU_CAP_DEVICE_STREAMING "NVML_DEVICE_VGPU_CAP_DEVICE_STREAMING" = 5
NVML_DEVICE_VGPU_CAP_MINI_QUARTER_GPU "NVML_DEVICE_VGPU_CAP_MINI_QUARTER_GPU" = 6
NVML_DEVICE_VGPU_CAP_COMPUTE_MEDIA_ENGINE_GPU "NVML_DEVICE_VGPU_CAP_COMPUTE_MEDIA_ENGINE_GPU" = 7
NVML_DEVICE_VGPU_CAP_WARM_UPDATE "NVML_DEVICE_VGPU_CAP_WARM_UPDATE" = 8
NVML_DEVICE_VGPU_CAP_HOMOGENEOUS_PLACEMENTS "NVML_DEVICE_VGPU_CAP_HOMOGENEOUS_PLACEMENTS" = 9
NVML_DEVICE_VGPU_CAP_MIG_TIMESLICING_SUPPORTED "NVML_DEVICE_VGPU_CAP_MIG_TIMESLICING_SUPPORTED" = 10
NVML_DEVICE_VGPU_CAP_MIG_TIMESLICING_ENABLED "NVML_DEVICE_VGPU_CAP_MIG_TIMESLICING_ENABLED" = 11
NVML_DEVICE_VGPU_CAP_COUNT "NVML_DEVICE_VGPU_CAP_COUNT"
ctypedef enum nvmlDeviceGpuRecoveryAction_t "nvmlDeviceGpuRecoveryAction_t":
NVML_GPU_RECOVERY_ACTION_NONE "NVML_GPU_RECOVERY_ACTION_NONE" = 0
NVML_GPU_RECOVERY_ACTION_GPU_RESET "NVML_GPU_RECOVERY_ACTION_GPU_RESET" = 1
NVML_GPU_RECOVERY_ACTION_NODE_REBOOT "NVML_GPU_RECOVERY_ACTION_NODE_REBOOT" = 2
NVML_GPU_RECOVERY_ACTION_DRAIN_P2P "NVML_GPU_RECOVERY_ACTION_DRAIN_P2P" = 3
NVML_GPU_RECOVERY_ACTION_DRAIN_AND_RESET "NVML_GPU_RECOVERY_ACTION_DRAIN_AND_RESET" = 4
ctypedef enum nvmlFanState_t "nvmlFanState_t":
NVML_FAN_NORMAL "NVML_FAN_NORMAL" = 0
NVML_FAN_FAILED "NVML_FAN_FAILED" = 1
ctypedef enum nvmlLedColor_t "nvmlLedColor_t":
NVML_LED_COLOR_GREEN "NVML_LED_COLOR_GREEN" = 0
NVML_LED_COLOR_AMBER "NVML_LED_COLOR_AMBER" = 1
ctypedef enum nvmlEncoderType_t "nvmlEncoderType_t":
NVML_ENCODER_QUERY_H264 "NVML_ENCODER_QUERY_H264" = 0x00
NVML_ENCODER_QUERY_HEVC "NVML_ENCODER_QUERY_HEVC" = 0x01
NVML_ENCODER_QUERY_AV1 "NVML_ENCODER_QUERY_AV1" = 0x02
NVML_ENCODER_QUERY_UNKNOWN "NVML_ENCODER_QUERY_UNKNOWN" = 0xFF
ctypedef enum nvmlFBCSessionType_t "nvmlFBCSessionType_t":
NVML_FBC_SESSION_TYPE_UNKNOWN "NVML_FBC_SESSION_TYPE_UNKNOWN" = 0
NVML_FBC_SESSION_TYPE_TOSYS "NVML_FBC_SESSION_TYPE_TOSYS"
NVML_FBC_SESSION_TYPE_CUDA "NVML_FBC_SESSION_TYPE_CUDA"
NVML_FBC_SESSION_TYPE_VID "NVML_FBC_SESSION_TYPE_VID"
NVML_FBC_SESSION_TYPE_HWENC "NVML_FBC_SESSION_TYPE_HWENC"
ctypedef enum nvmlDetachGpuState_t "nvmlDetachGpuState_t":
NVML_DETACH_GPU_KEEP "NVML_DETACH_GPU_KEEP" = 0
NVML_DETACH_GPU_REMOVE "NVML_DETACH_GPU_REMOVE"
ctypedef enum nvmlPcieLinkState_t "nvmlPcieLinkState_t":
NVML_PCIE_LINK_KEEP "NVML_PCIE_LINK_KEEP" = 0
NVML_PCIE_LINK_SHUT_DOWN "NVML_PCIE_LINK_SHUT_DOWN"
ctypedef enum nvmlClockLimitId_t "nvmlClockLimitId_t":
NVML_CLOCK_LIMIT_ID_RANGE_START "NVML_CLOCK_LIMIT_ID_RANGE_START" = 0xffffff00
NVML_CLOCK_LIMIT_ID_TDP "NVML_CLOCK_LIMIT_ID_TDP"
NVML_CLOCK_LIMIT_ID_UNLIMITED "NVML_CLOCK_LIMIT_ID_UNLIMITED"
ctypedef enum nvmlVgpuVmCompatibility_t "nvmlVgpuVmCompatibility_t":
NVML_VGPU_VM_COMPATIBILITY_NONE "NVML_VGPU_VM_COMPATIBILITY_NONE" = 0x0
NVML_VGPU_VM_COMPATIBILITY_COLD "NVML_VGPU_VM_COMPATIBILITY_COLD" = 0x1
NVML_VGPU_VM_COMPATIBILITY_HIBERNATE "NVML_VGPU_VM_COMPATIBILITY_HIBERNATE" = 0x2
NVML_VGPU_VM_COMPATIBILITY_SLEEP "NVML_VGPU_VM_COMPATIBILITY_SLEEP" = 0x4
NVML_VGPU_VM_COMPATIBILITY_LIVE "NVML_VGPU_VM_COMPATIBILITY_LIVE" = 0x8
ctypedef enum nvmlVgpuPgpuCompatibilityLimitCode_t "nvmlVgpuPgpuCompatibilityLimitCode_t":
NVML_VGPU_COMPATIBILITY_LIMIT_NONE "NVML_VGPU_COMPATIBILITY_LIMIT_NONE" = 0x0
NVML_VGPU_COMPATIBILITY_LIMIT_HOST_DRIVER "NVML_VGPU_COMPATIBILITY_LIMIT_HOST_DRIVER" = 0x1
NVML_VGPU_COMPATIBILITY_LIMIT_GUEST_DRIVER "NVML_VGPU_COMPATIBILITY_LIMIT_GUEST_DRIVER" = 0x2
NVML_VGPU_COMPATIBILITY_LIMIT_GPU "NVML_VGPU_COMPATIBILITY_LIMIT_GPU" = 0x4
NVML_VGPU_COMPATIBILITY_LIMIT_OTHER "NVML_VGPU_COMPATIBILITY_LIMIT_OTHER" = 0x80000000
ctypedef enum nvmlGpmMetricId_t "nvmlGpmMetricId_t":
NVML_GPM_METRIC_GRAPHICS_UTIL "NVML_GPM_METRIC_GRAPHICS_UTIL" = 1
NVML_GPM_METRIC_SM_UTIL "NVML_GPM_METRIC_SM_UTIL" = 2
NVML_GPM_METRIC_SM_OCCUPANCY "NVML_GPM_METRIC_SM_OCCUPANCY" = 3
NVML_GPM_METRIC_INTEGER_UTIL "NVML_GPM_METRIC_INTEGER_UTIL" = 4
NVML_GPM_METRIC_ANY_TENSOR_UTIL "NVML_GPM_METRIC_ANY_TENSOR_UTIL" = 5
NVML_GPM_METRIC_DFMA_TENSOR_UTIL "NVML_GPM_METRIC_DFMA_TENSOR_UTIL" = 6
NVML_GPM_METRIC_HMMA_TENSOR_UTIL "NVML_GPM_METRIC_HMMA_TENSOR_UTIL" = 7
NVML_GPM_METRIC_DMMA_TENSOR_UTIL "NVML_GPM_METRIC_DMMA_TENSOR_UTIL" = 8
NVML_GPM_METRIC_IMMA_TENSOR_UTIL "NVML_GPM_METRIC_IMMA_TENSOR_UTIL" = 9
NVML_GPM_METRIC_DRAM_BW_UTIL "NVML_GPM_METRIC_DRAM_BW_UTIL" = 10
NVML_GPM_METRIC_FP64_UTIL "NVML_GPM_METRIC_FP64_UTIL" = 11
NVML_GPM_METRIC_FP32_UTIL "NVML_GPM_METRIC_FP32_UTIL" = 12
NVML_GPM_METRIC_FP16_UTIL "NVML_GPM_METRIC_FP16_UTIL" = 13
NVML_GPM_METRIC_PCIE_TX_PER_SEC "NVML_GPM_METRIC_PCIE_TX_PER_SEC" = 20
NVML_GPM_METRIC_PCIE_RX_PER_SEC "NVML_GPM_METRIC_PCIE_RX_PER_SEC" = 21
NVML_GPM_METRIC_NVDEC_0_UTIL "NVML_GPM_METRIC_NVDEC_0_UTIL" = 30
NVML_GPM_METRIC_NVDEC_1_UTIL "NVML_GPM_METRIC_NVDEC_1_UTIL" = 31
NVML_GPM_METRIC_NVDEC_2_UTIL "NVML_GPM_METRIC_NVDEC_2_UTIL" = 32
NVML_GPM_METRIC_NVDEC_3_UTIL "NVML_GPM_METRIC_NVDEC_3_UTIL" = 33
NVML_GPM_METRIC_NVDEC_4_UTIL "NVML_GPM_METRIC_NVDEC_4_UTIL" = 34
NVML_GPM_METRIC_NVDEC_5_UTIL "NVML_GPM_METRIC_NVDEC_5_UTIL" = 35
NVML_GPM_METRIC_NVDEC_6_UTIL "NVML_GPM_METRIC_NVDEC_6_UTIL" = 36
NVML_GPM_METRIC_NVDEC_7_UTIL "NVML_GPM_METRIC_NVDEC_7_UTIL" = 37
NVML_GPM_METRIC_NVJPG_0_UTIL "NVML_GPM_METRIC_NVJPG_0_UTIL" = 40
NVML_GPM_METRIC_NVJPG_1_UTIL "NVML_GPM_METRIC_NVJPG_1_UTIL" = 41
NVML_GPM_METRIC_NVJPG_2_UTIL "NVML_GPM_METRIC_NVJPG_2_UTIL" = 42
NVML_GPM_METRIC_NVJPG_3_UTIL "NVML_GPM_METRIC_NVJPG_3_UTIL" = 43
NVML_GPM_METRIC_NVJPG_4_UTIL "NVML_GPM_METRIC_NVJPG_4_UTIL" = 44
NVML_GPM_METRIC_NVJPG_5_UTIL "NVML_GPM_METRIC_NVJPG_5_UTIL" = 45
NVML_GPM_METRIC_NVJPG_6_UTIL "NVML_GPM_METRIC_NVJPG_6_UTIL" = 46
NVML_GPM_METRIC_NVJPG_7_UTIL "NVML_GPM_METRIC_NVJPG_7_UTIL" = 47
NVML_GPM_METRIC_NVOFA_0_UTIL "NVML_GPM_METRIC_NVOFA_0_UTIL" = 50
NVML_GPM_METRIC_NVOFA_1_UTIL "NVML_GPM_METRIC_NVOFA_1_UTIL" = 51
NVML_GPM_METRIC_NVLINK_TOTAL_RX_PER_SEC "NVML_GPM_METRIC_NVLINK_TOTAL_RX_PER_SEC" = 60
NVML_GPM_METRIC_NVLINK_TOTAL_TX_PER_SEC "NVML_GPM_METRIC_NVLINK_TOTAL_TX_PER_SEC" = 61
NVML_GPM_METRIC_NVLINK_L0_RX_PER_SEC "NVML_GPM_METRIC_NVLINK_L0_RX_PER_SEC" = 62
NVML_GPM_METRIC_NVLINK_L0_TX_PER_SEC "NVML_GPM_METRIC_NVLINK_L0_TX_PER_SEC" = 63
NVML_GPM_METRIC_NVLINK_L1_RX_PER_SEC "NVML_GPM_METRIC_NVLINK_L1_RX_PER_SEC" = 64
NVML_GPM_METRIC_NVLINK_L1_TX_PER_SEC "NVML_GPM_METRIC_NVLINK_L1_TX_PER_SEC" = 65
NVML_GPM_METRIC_NVLINK_L2_RX_PER_SEC "NVML_GPM_METRIC_NVLINK_L2_RX_PER_SEC" = 66
NVML_GPM_METRIC_NVLINK_L2_TX_PER_SEC "NVML_GPM_METRIC_NVLINK_L2_TX_PER_SEC" = 67
NVML_GPM_METRIC_NVLINK_L3_RX_PER_SEC "NVML_GPM_METRIC_NVLINK_L3_RX_PER_SEC" = 68
NVML_GPM_METRIC_NVLINK_L3_TX_PER_SEC "NVML_GPM_METRIC_NVLINK_L3_TX_PER_SEC" = 69
NVML_GPM_METRIC_NVLINK_L4_RX_PER_SEC "NVML_GPM_METRIC_NVLINK_L4_RX_PER_SEC" = 70
NVML_GPM_METRIC_NVLINK_L4_TX_PER_SEC "NVML_GPM_METRIC_NVLINK_L4_TX_PER_SEC" = 71
NVML_GPM_METRIC_NVLINK_L5_RX_PER_SEC "NVML_GPM_METRIC_NVLINK_L5_RX_PER_SEC" = 72
NVML_GPM_METRIC_NVLINK_L5_TX_PER_SEC "NVML_GPM_METRIC_NVLINK_L5_TX_PER_SEC" = 73
NVML_GPM_METRIC_NVLINK_L6_RX_PER_SEC "NVML_GPM_METRIC_NVLINK_L6_RX_PER_SEC" = 74
NVML_GPM_METRIC_NVLINK_L6_TX_PER_SEC "NVML_GPM_METRIC_NVLINK_L6_TX_PER_SEC" = 75
NVML_GPM_METRIC_NVLINK_L7_RX_PER_SEC "NVML_GPM_METRIC_NVLINK_L7_RX_PER_SEC" = 76
NVML_GPM_METRIC_NVLINK_L7_TX_PER_SEC "NVML_GPM_METRIC_NVLINK_L7_TX_PER_SEC" = 77
NVML_GPM_METRIC_NVLINK_L8_RX_PER_SEC "NVML_GPM_METRIC_NVLINK_L8_RX_PER_SEC" = 78
NVML_GPM_METRIC_NVLINK_L8_TX_PER_SEC "NVML_GPM_METRIC_NVLINK_L8_TX_PER_SEC" = 79
NVML_GPM_METRIC_NVLINK_L9_RX_PER_SEC "NVML_GPM_METRIC_NVLINK_L9_RX_PER_SEC" = 80
NVML_GPM_METRIC_NVLINK_L9_TX_PER_SEC "NVML_GPM_METRIC_NVLINK_L9_TX_PER_SEC" = 81
NVML_GPM_METRIC_NVLINK_L10_RX_PER_SEC "NVML_GPM_METRIC_NVLINK_L10_RX_PER_SEC" = 82
NVML_GPM_METRIC_NVLINK_L10_TX_PER_SEC "NVML_GPM_METRIC_NVLINK_L10_TX_PER_SEC" = 83
NVML_GPM_METRIC_NVLINK_L11_RX_PER_SEC "NVML_GPM_METRIC_NVLINK_L11_RX_PER_SEC" = 84
NVML_GPM_METRIC_NVLINK_L11_TX_PER_SEC "NVML_GPM_METRIC_NVLINK_L11_TX_PER_SEC" = 85
NVML_GPM_METRIC_NVLINK_L12_RX_PER_SEC "NVML_GPM_METRIC_NVLINK_L12_RX_PER_SEC" = 86
NVML_GPM_METRIC_NVLINK_L12_TX_PER_SEC "NVML_GPM_METRIC_NVLINK_L12_TX_PER_SEC" = 87
NVML_GPM_METRIC_NVLINK_L13_RX_PER_SEC "NVML_GPM_METRIC_NVLINK_L13_RX_PER_SEC" = 88
NVML_GPM_METRIC_NVLINK_L13_TX_PER_SEC "NVML_GPM_METRIC_NVLINK_L13_TX_PER_SEC" = 89
NVML_GPM_METRIC_NVLINK_L14_RX_PER_SEC "NVML_GPM_METRIC_NVLINK_L14_RX_PER_SEC" = 90
NVML_GPM_METRIC_NVLINK_L14_TX_PER_SEC "NVML_GPM_METRIC_NVLINK_L14_TX_PER_SEC" = 91
NVML_GPM_METRIC_NVLINK_L15_RX_PER_SEC "NVML_GPM_METRIC_NVLINK_L15_RX_PER_SEC" = 92
NVML_GPM_METRIC_NVLINK_L15_TX_PER_SEC "NVML_GPM_METRIC_NVLINK_L15_TX_PER_SEC" = 93
NVML_GPM_METRIC_NVLINK_L16_RX_PER_SEC "NVML_GPM_METRIC_NVLINK_L16_RX_PER_SEC" = 94
NVML_GPM_METRIC_NVLINK_L16_TX_PER_SEC "NVML_GPM_METRIC_NVLINK_L16_TX_PER_SEC" = 95
NVML_GPM_METRIC_NVLINK_L17_RX_PER_SEC "NVML_GPM_METRIC_NVLINK_L17_RX_PER_SEC" = 96
NVML_GPM_METRIC_NVLINK_L17_TX_PER_SEC "NVML_GPM_METRIC_NVLINK_L17_TX_PER_SEC" = 97
NVML_GPM_METRIC_C2C_TOTAL_TX_PER_SEC "NVML_GPM_METRIC_C2C_TOTAL_TX_PER_SEC" = 100
NVML_GPM_METRIC_C2C_TOTAL_RX_PER_SEC "NVML_GPM_METRIC_C2C_TOTAL_RX_PER_SEC" = 101
NVML_GPM_METRIC_C2C_DATA_TX_PER_SEC "NVML_GPM_METRIC_C2C_DATA_TX_PER_SEC" = 102
NVML_GPM_METRIC_C2C_DATA_RX_PER_SEC "NVML_GPM_METRIC_C2C_DATA_RX_PER_SEC" = 103
NVML_GPM_METRIC_C2C_LINK0_TOTAL_TX_PER_SEC "NVML_GPM_METRIC_C2C_LINK0_TOTAL_TX_PER_SEC" = 104
NVML_GPM_METRIC_C2C_LINK0_TOTAL_RX_PER_SEC "NVML_GPM_METRIC_C2C_LINK0_TOTAL_RX_PER_SEC" = 105
NVML_GPM_METRIC_C2C_LINK0_DATA_TX_PER_SEC "NVML_GPM_METRIC_C2C_LINK0_DATA_TX_PER_SEC" = 106
NVML_GPM_METRIC_C2C_LINK0_DATA_RX_PER_SEC "NVML_GPM_METRIC_C2C_LINK0_DATA_RX_PER_SEC" = 107
NVML_GPM_METRIC_C2C_LINK1_TOTAL_TX_PER_SEC "NVML_GPM_METRIC_C2C_LINK1_TOTAL_TX_PER_SEC" = 108
NVML_GPM_METRIC_C2C_LINK1_TOTAL_RX_PER_SEC "NVML_GPM_METRIC_C2C_LINK1_TOTAL_RX_PER_SEC" = 109
NVML_GPM_METRIC_C2C_LINK1_DATA_TX_PER_SEC "NVML_GPM_METRIC_C2C_LINK1_DATA_TX_PER_SEC" = 110
NVML_GPM_METRIC_C2C_LINK1_DATA_RX_PER_SEC "NVML_GPM_METRIC_C2C_LINK1_DATA_RX_PER_SEC" = 111
NVML_GPM_METRIC_C2C_LINK2_TOTAL_TX_PER_SEC "NVML_GPM_METRIC_C2C_LINK2_TOTAL_TX_PER_SEC" = 112
NVML_GPM_METRIC_C2C_LINK2_TOTAL_RX_PER_SEC "NVML_GPM_METRIC_C2C_LINK2_TOTAL_RX_PER_SEC" = 113
NVML_GPM_METRIC_C2C_LINK2_DATA_TX_PER_SEC "NVML_GPM_METRIC_C2C_LINK2_DATA_TX_PER_SEC" = 114
NVML_GPM_METRIC_C2C_LINK2_DATA_RX_PER_SEC "NVML_GPM_METRIC_C2C_LINK2_DATA_RX_PER_SEC" = 115
NVML_GPM_METRIC_C2C_LINK3_TOTAL_TX_PER_SEC "NVML_GPM_METRIC_C2C_LINK3_TOTAL_TX_PER_SEC" = 116
NVML_GPM_METRIC_C2C_LINK3_TOTAL_RX_PER_SEC "NVML_GPM_METRIC_C2C_LINK3_TOTAL_RX_PER_SEC" = 117
NVML_GPM_METRIC_C2C_LINK3_DATA_TX_PER_SEC "NVML_GPM_METRIC_C2C_LINK3_DATA_TX_PER_SEC" = 118
NVML_GPM_METRIC_C2C_LINK3_DATA_RX_PER_SEC "NVML_GPM_METRIC_C2C_LINK3_DATA_RX_PER_SEC" = 119
NVML_GPM_METRIC_C2C_LINK4_TOTAL_TX_PER_SEC "NVML_GPM_METRIC_C2C_LINK4_TOTAL_TX_PER_SEC" = 120
NVML_GPM_METRIC_C2C_LINK4_TOTAL_RX_PER_SEC "NVML_GPM_METRIC_C2C_LINK4_TOTAL_RX_PER_SEC" = 121
NVML_GPM_METRIC_C2C_LINK4_DATA_TX_PER_SEC "NVML_GPM_METRIC_C2C_LINK4_DATA_TX_PER_SEC" = 122
NVML_GPM_METRIC_C2C_LINK4_DATA_RX_PER_SEC "NVML_GPM_METRIC_C2C_LINK4_DATA_RX_PER_SEC" = 123
NVML_GPM_METRIC_C2C_LINK5_TOTAL_TX_PER_SEC "NVML_GPM_METRIC_C2C_LINK5_TOTAL_TX_PER_SEC" = 124
NVML_GPM_METRIC_C2C_LINK5_TOTAL_RX_PER_SEC "NVML_GPM_METRIC_C2C_LINK5_TOTAL_RX_PER_SEC" = 125
NVML_GPM_METRIC_C2C_LINK5_DATA_TX_PER_SEC "NVML_GPM_METRIC_C2C_LINK5_DATA_TX_PER_SEC" = 126
NVML_GPM_METRIC_C2C_LINK5_DATA_RX_PER_SEC "NVML_GPM_METRIC_C2C_LINK5_DATA_RX_PER_SEC" = 127
NVML_GPM_METRIC_C2C_LINK6_TOTAL_TX_PER_SEC "NVML_GPM_METRIC_C2C_LINK6_TOTAL_TX_PER_SEC" = 128
NVML_GPM_METRIC_C2C_LINK6_TOTAL_RX_PER_SEC "NVML_GPM_METRIC_C2C_LINK6_TOTAL_RX_PER_SEC" = 129
NVML_GPM_METRIC_C2C_LINK6_DATA_TX_PER_SEC "NVML_GPM_METRIC_C2C_LINK6_DATA_TX_PER_SEC" = 130
NVML_GPM_METRIC_C2C_LINK6_DATA_RX_PER_SEC "NVML_GPM_METRIC_C2C_LINK6_DATA_RX_PER_SEC" = 131
NVML_GPM_METRIC_C2C_LINK7_TOTAL_TX_PER_SEC "NVML_GPM_METRIC_C2C_LINK7_TOTAL_TX_PER_SEC" = 132
NVML_GPM_METRIC_C2C_LINK7_TOTAL_RX_PER_SEC "NVML_GPM_METRIC_C2C_LINK7_TOTAL_RX_PER_SEC" = 133
NVML_GPM_METRIC_C2C_LINK7_DATA_TX_PER_SEC "NVML_GPM_METRIC_C2C_LINK7_DATA_TX_PER_SEC" = 134
NVML_GPM_METRIC_C2C_LINK7_DATA_RX_PER_SEC "NVML_GPM_METRIC_C2C_LINK7_DATA_RX_PER_SEC" = 135
NVML_GPM_METRIC_C2C_LINK8_TOTAL_TX_PER_SEC "NVML_GPM_METRIC_C2C_LINK8_TOTAL_TX_PER_SEC" = 136
NVML_GPM_METRIC_C2C_LINK8_TOTAL_RX_PER_SEC "NVML_GPM_METRIC_C2C_LINK8_TOTAL_RX_PER_SEC" = 137
NVML_GPM_METRIC_C2C_LINK8_DATA_TX_PER_SEC "NVML_GPM_METRIC_C2C_LINK8_DATA_TX_PER_SEC" = 138
NVML_GPM_METRIC_C2C_LINK8_DATA_RX_PER_SEC "NVML_GPM_METRIC_C2C_LINK8_DATA_RX_PER_SEC" = 139
NVML_GPM_METRIC_C2C_LINK9_TOTAL_TX_PER_SEC "NVML_GPM_METRIC_C2C_LINK9_TOTAL_TX_PER_SEC" = 140
NVML_GPM_METRIC_C2C_LINK9_TOTAL_RX_PER_SEC "NVML_GPM_METRIC_C2C_LINK9_TOTAL_RX_PER_SEC" = 141
NVML_GPM_METRIC_C2C_LINK9_DATA_TX_PER_SEC "NVML_GPM_METRIC_C2C_LINK9_DATA_TX_PER_SEC" = 142
NVML_GPM_METRIC_C2C_LINK9_DATA_RX_PER_SEC "NVML_GPM_METRIC_C2C_LINK9_DATA_RX_PER_SEC" = 143
NVML_GPM_METRIC_C2C_LINK10_TOTAL_TX_PER_SEC "NVML_GPM_METRIC_C2C_LINK10_TOTAL_TX_PER_SEC" = 144
NVML_GPM_METRIC_C2C_LINK10_TOTAL_RX_PER_SEC "NVML_GPM_METRIC_C2C_LINK10_TOTAL_RX_PER_SEC" = 145
NVML_GPM_METRIC_C2C_LINK10_DATA_TX_PER_SEC "NVML_GPM_METRIC_C2C_LINK10_DATA_TX_PER_SEC" = 146
NVML_GPM_METRIC_C2C_LINK10_DATA_RX_PER_SEC "NVML_GPM_METRIC_C2C_LINK10_DATA_RX_PER_SEC" = 147
NVML_GPM_METRIC_C2C_LINK11_TOTAL_TX_PER_SEC "NVML_GPM_METRIC_C2C_LINK11_TOTAL_TX_PER_SEC" = 148
NVML_GPM_METRIC_C2C_LINK11_TOTAL_RX_PER_SEC "NVML_GPM_METRIC_C2C_LINK11_TOTAL_RX_PER_SEC" = 149
NVML_GPM_METRIC_C2C_LINK11_DATA_TX_PER_SEC "NVML_GPM_METRIC_C2C_LINK11_DATA_TX_PER_SEC" = 150
NVML_GPM_METRIC_C2C_LINK11_DATA_RX_PER_SEC "NVML_GPM_METRIC_C2C_LINK11_DATA_RX_PER_SEC" = 151
NVML_GPM_METRIC_C2C_LINK12_TOTAL_TX_PER_SEC "NVML_GPM_METRIC_C2C_LINK12_TOTAL_TX_PER_SEC" = 152
NVML_GPM_METRIC_C2C_LINK12_TOTAL_RX_PER_SEC "NVML_GPM_METRIC_C2C_LINK12_TOTAL_RX_PER_SEC" = 153
NVML_GPM_METRIC_C2C_LINK12_DATA_TX_PER_SEC "NVML_GPM_METRIC_C2C_LINK12_DATA_TX_PER_SEC" = 154
NVML_GPM_METRIC_C2C_LINK12_DATA_RX_PER_SEC "NVML_GPM_METRIC_C2C_LINK12_DATA_RX_PER_SEC" = 155
NVML_GPM_METRIC_C2C_LINK13_TOTAL_TX_PER_SEC "NVML_GPM_METRIC_C2C_LINK13_TOTAL_TX_PER_SEC" = 156
NVML_GPM_METRIC_C2C_LINK13_TOTAL_RX_PER_SEC "NVML_GPM_METRIC_C2C_LINK13_TOTAL_RX_PER_SEC" = 157
NVML_GPM_METRIC_C2C_LINK13_DATA_TX_PER_SEC "NVML_GPM_METRIC_C2C_LINK13_DATA_TX_PER_SEC" = 158
NVML_GPM_METRIC_C2C_LINK13_DATA_RX_PER_SEC "NVML_GPM_METRIC_C2C_LINK13_DATA_RX_PER_SEC" = 159
NVML_GPM_METRIC_HOSTMEM_CACHE_HIT "NVML_GPM_METRIC_HOSTMEM_CACHE_HIT" = 160
NVML_GPM_METRIC_HOSTMEM_CACHE_MISS "NVML_GPM_METRIC_HOSTMEM_CACHE_MISS" = 161
NVML_GPM_METRIC_PEERMEM_CACHE_HIT "NVML_GPM_METRIC_PEERMEM_CACHE_HIT" = 162
NVML_GPM_METRIC_PEERMEM_CACHE_MISS "NVML_GPM_METRIC_PEERMEM_CACHE_MISS" = 163
NVML_GPM_METRIC_DRAM_CACHE_HIT "NVML_GPM_METRIC_DRAM_CACHE_HIT" = 164
NVML_GPM_METRIC_DRAM_CACHE_MISS "NVML_GPM_METRIC_DRAM_CACHE_MISS" = 165
NVML_GPM_METRIC_NVENC_0_UTIL "NVML_GPM_METRIC_NVENC_0_UTIL" = 166
NVML_GPM_METRIC_NVENC_1_UTIL "NVML_GPM_METRIC_NVENC_1_UTIL" = 167
NVML_GPM_METRIC_NVENC_2_UTIL "NVML_GPM_METRIC_NVENC_2_UTIL" = 168
NVML_GPM_METRIC_NVENC_3_UTIL "NVML_GPM_METRIC_NVENC_3_UTIL" = 169
NVML_GPM_METRIC_GR0_CTXSW_CYCLES_ELAPSED "NVML_GPM_METRIC_GR0_CTXSW_CYCLES_ELAPSED" = 170
NVML_GPM_METRIC_GR0_CTXSW_CYCLES_ACTIVE "NVML_GPM_METRIC_GR0_CTXSW_CYCLES_ACTIVE" = 171
NVML_GPM_METRIC_GR0_CTXSW_REQUESTS "NVML_GPM_METRIC_GR0_CTXSW_REQUESTS" = 172
NVML_GPM_METRIC_GR0_CTXSW_CYCLES_PER_REQ "NVML_GPM_METRIC_GR0_CTXSW_CYCLES_PER_REQ" = 173
NVML_GPM_METRIC_GR0_CTXSW_ACTIVE_PCT "NVML_GPM_METRIC_GR0_CTXSW_ACTIVE_PCT" = 174
NVML_GPM_METRIC_GR1_CTXSW_CYCLES_ELAPSED "NVML_GPM_METRIC_GR1_CTXSW_CYCLES_ELAPSED" = 175
NVML_GPM_METRIC_GR1_CTXSW_CYCLES_ACTIVE "NVML_GPM_METRIC_GR1_CTXSW_CYCLES_ACTIVE" = 176
NVML_GPM_METRIC_GR1_CTXSW_REQUESTS "NVML_GPM_METRIC_GR1_CTXSW_REQUESTS" = 177
NVML_GPM_METRIC_GR1_CTXSW_CYCLES_PER_REQ "NVML_GPM_METRIC_GR1_CTXSW_CYCLES_PER_REQ" = 178
NVML_GPM_METRIC_GR1_CTXSW_ACTIVE_PCT "NVML_GPM_METRIC_GR1_CTXSW_ACTIVE_PCT" = 179
NVML_GPM_METRIC_GR2_CTXSW_CYCLES_ELAPSED "NVML_GPM_METRIC_GR2_CTXSW_CYCLES_ELAPSED" = 180
NVML_GPM_METRIC_GR2_CTXSW_CYCLES_ACTIVE "NVML_GPM_METRIC_GR2_CTXSW_CYCLES_ACTIVE" = 181
NVML_GPM_METRIC_GR2_CTXSW_REQUESTS "NVML_GPM_METRIC_GR2_CTXSW_REQUESTS" = 182
NVML_GPM_METRIC_GR2_CTXSW_CYCLES_PER_REQ "NVML_GPM_METRIC_GR2_CTXSW_CYCLES_PER_REQ" = 183
NVML_GPM_METRIC_GR2_CTXSW_ACTIVE_PCT "NVML_GPM_METRIC_GR2_CTXSW_ACTIVE_PCT" = 184
NVML_GPM_METRIC_GR3_CTXSW_CYCLES_ELAPSED "NVML_GPM_METRIC_GR3_CTXSW_CYCLES_ELAPSED" = 185
NVML_GPM_METRIC_GR3_CTXSW_CYCLES_ACTIVE "NVML_GPM_METRIC_GR3_CTXSW_CYCLES_ACTIVE" = 186
NVML_GPM_METRIC_GR3_CTXSW_REQUESTS "NVML_GPM_METRIC_GR3_CTXSW_REQUESTS" = 187
NVML_GPM_METRIC_GR3_CTXSW_CYCLES_PER_REQ "NVML_GPM_METRIC_GR3_CTXSW_CYCLES_PER_REQ" = 188
NVML_GPM_METRIC_GR3_CTXSW_ACTIVE_PCT "NVML_GPM_METRIC_GR3_CTXSW_ACTIVE_PCT" = 189
NVML_GPM_METRIC_GR4_CTXSW_CYCLES_ELAPSED "NVML_GPM_METRIC_GR4_CTXSW_CYCLES_ELAPSED" = 190
NVML_GPM_METRIC_GR4_CTXSW_CYCLES_ACTIVE "NVML_GPM_METRIC_GR4_CTXSW_CYCLES_ACTIVE" = 191
NVML_GPM_METRIC_GR4_CTXSW_REQUESTS "NVML_GPM_METRIC_GR4_CTXSW_REQUESTS" = 192
NVML_GPM_METRIC_GR4_CTXSW_CYCLES_PER_REQ "NVML_GPM_METRIC_GR4_CTXSW_CYCLES_PER_REQ" = 193
NVML_GPM_METRIC_GR4_CTXSW_ACTIVE_PCT "NVML_GPM_METRIC_GR4_CTXSW_ACTIVE_PCT" = 194
NVML_GPM_METRIC_GR5_CTXSW_CYCLES_ELAPSED "NVML_GPM_METRIC_GR5_CTXSW_CYCLES_ELAPSED" = 195
NVML_GPM_METRIC_GR5_CTXSW_CYCLES_ACTIVE "NVML_GPM_METRIC_GR5_CTXSW_CYCLES_ACTIVE" = 196
NVML_GPM_METRIC_GR5_CTXSW_REQUESTS "NVML_GPM_METRIC_GR5_CTXSW_REQUESTS" = 197
NVML_GPM_METRIC_GR5_CTXSW_CYCLES_PER_REQ "NVML_GPM_METRIC_GR5_CTXSW_CYCLES_PER_REQ" = 198
NVML_GPM_METRIC_GR5_CTXSW_ACTIVE_PCT "NVML_GPM_METRIC_GR5_CTXSW_ACTIVE_PCT" = 199
NVML_GPM_METRIC_GR6_CTXSW_CYCLES_ELAPSED "NVML_GPM_METRIC_GR6_CTXSW_CYCLES_ELAPSED" = 200
NVML_GPM_METRIC_GR6_CTXSW_CYCLES_ACTIVE "NVML_GPM_METRIC_GR6_CTXSW_CYCLES_ACTIVE" = 201
NVML_GPM_METRIC_GR6_CTXSW_REQUESTS "NVML_GPM_METRIC_GR6_CTXSW_REQUESTS" = 202
NVML_GPM_METRIC_GR6_CTXSW_CYCLES_PER_REQ "NVML_GPM_METRIC_GR6_CTXSW_CYCLES_PER_REQ" = 203
NVML_GPM_METRIC_GR6_CTXSW_ACTIVE_PCT "NVML_GPM_METRIC_GR6_CTXSW_ACTIVE_PCT" = 204
NVML_GPM_METRIC_GR7_CTXSW_CYCLES_ELAPSED "NVML_GPM_METRIC_GR7_CTXSW_CYCLES_ELAPSED" = 205
NVML_GPM_METRIC_GR7_CTXSW_CYCLES_ACTIVE "NVML_GPM_METRIC_GR7_CTXSW_CYCLES_ACTIVE" = 206
NVML_GPM_METRIC_GR7_CTXSW_REQUESTS "NVML_GPM_METRIC_GR7_CTXSW_REQUESTS" = 207
NVML_GPM_METRIC_GR7_CTXSW_CYCLES_PER_REQ "NVML_GPM_METRIC_GR7_CTXSW_CYCLES_PER_REQ" = 208
NVML_GPM_METRIC_GR7_CTXSW_ACTIVE_PCT "NVML_GPM_METRIC_GR7_CTXSW_ACTIVE_PCT" = 209
NVML_GPM_METRIC_SM_CYCLES_ELAPSED "NVML_GPM_METRIC_SM_CYCLES_ELAPSED" = 248
NVML_GPM_METRIC_SM_CYCLES_ACTIVE "NVML_GPM_METRIC_SM_CYCLES_ACTIVE" = 249
NVML_GPM_METRIC_MMA_CYCLES_ACTIVE "NVML_GPM_METRIC_MMA_CYCLES_ACTIVE" = 250
NVML_GPM_METRIC_DMMA_CYCLES_ACTIVE "NVML_GPM_METRIC_DMMA_CYCLES_ACTIVE" = 251
NVML_GPM_METRIC_HMMA_CYCLES_ACTIVE "NVML_GPM_METRIC_HMMA_CYCLES_ACTIVE" = 252
NVML_GPM_METRIC_IMMA_CYCLES_ACTIVE "NVML_GPM_METRIC_IMMA_CYCLES_ACTIVE" = 253
NVML_GPM_METRIC_DFMA_CYCLES_ACTIVE "NVML_GPM_METRIC_DFMA_CYCLES_ACTIVE" = 254
NVML_GPM_METRIC_PCIE_TX "NVML_GPM_METRIC_PCIE_TX" = 255
NVML_GPM_METRIC_PCIE_RX "NVML_GPM_METRIC_PCIE_RX" = 256
NVML_GPM_METRIC_INTEGER_CYCLES_ACTIVE "NVML_GPM_METRIC_INTEGER_CYCLES_ACTIVE" = 257
NVML_GPM_METRIC_FP64_CYCLES_ACTIVE "NVML_GPM_METRIC_FP64_CYCLES_ACTIVE" = 258
NVML_GPM_METRIC_FP32_CYCLES_ACTIVE "NVML_GPM_METRIC_FP32_CYCLES_ACTIVE" = 259
NVML_GPM_METRIC_FP16_CYCLES_ACTIVE "NVML_GPM_METRIC_FP16_CYCLES_ACTIVE" = 260
NVML_GPM_METRIC_NVLINK_L0_RX "NVML_GPM_METRIC_NVLINK_L0_RX" = 261
NVML_GPM_METRIC_NVLINK_L0_TX "NVML_GPM_METRIC_NVLINK_L0_TX" = 262
NVML_GPM_METRIC_NVLINK_L1_RX "NVML_GPM_METRIC_NVLINK_L1_RX" = 263
NVML_GPM_METRIC_NVLINK_L1_TX "NVML_GPM_METRIC_NVLINK_L1_TX" = 264
NVML_GPM_METRIC_NVLINK_L2_RX "NVML_GPM_METRIC_NVLINK_L2_RX" = 265
NVML_GPM_METRIC_NVLINK_L2_TX "NVML_GPM_METRIC_NVLINK_L2_TX" = 266
NVML_GPM_METRIC_NVLINK_L3_RX "NVML_GPM_METRIC_NVLINK_L3_RX" = 267
NVML_GPM_METRIC_NVLINK_L3_TX "NVML_GPM_METRIC_NVLINK_L3_TX" = 268
NVML_GPM_METRIC_NVLINK_L4_RX "NVML_GPM_METRIC_NVLINK_L4_RX" = 269
NVML_GPM_METRIC_NVLINK_L4_TX "NVML_GPM_METRIC_NVLINK_L4_TX" = 270
NVML_GPM_METRIC_NVLINK_L5_RX "NVML_GPM_METRIC_NVLINK_L5_RX" = 271
NVML_GPM_METRIC_NVLINK_L5_TX "NVML_GPM_METRIC_NVLINK_L5_TX" = 272
NVML_GPM_METRIC_NVLINK_L6_RX "NVML_GPM_METRIC_NVLINK_L6_RX" = 273
NVML_GPM_METRIC_NVLINK_L6_TX "NVML_GPM_METRIC_NVLINK_L6_TX" = 274
NVML_GPM_METRIC_NVLINK_L7_RX "NVML_GPM_METRIC_NVLINK_L7_RX" = 275
NVML_GPM_METRIC_NVLINK_L7_TX "NVML_GPM_METRIC_NVLINK_L7_TX" = 276
NVML_GPM_METRIC_NVLINK_L8_RX "NVML_GPM_METRIC_NVLINK_L8_RX" = 277
NVML_GPM_METRIC_NVLINK_L8_TX "NVML_GPM_METRIC_NVLINK_L8_TX" = 278
NVML_GPM_METRIC_NVLINK_L9_RX "NVML_GPM_METRIC_NVLINK_L9_RX" = 279
NVML_GPM_METRIC_NVLINK_L9_TX "NVML_GPM_METRIC_NVLINK_L9_TX" = 280
NVML_GPM_METRIC_NVLINK_L10_RX "NVML_GPM_METRIC_NVLINK_L10_RX" = 281
NVML_GPM_METRIC_NVLINK_L10_TX "NVML_GPM_METRIC_NVLINK_L10_TX" = 282
NVML_GPM_METRIC_NVLINK_L11_RX "NVML_GPM_METRIC_NVLINK_L11_RX" = 283
NVML_GPM_METRIC_NVLINK_L11_TX "NVML_GPM_METRIC_NVLINK_L11_TX" = 284
NVML_GPM_METRIC_NVLINK_L12_RX "NVML_GPM_METRIC_NVLINK_L12_RX" = 285
NVML_GPM_METRIC_NVLINK_L12_TX "NVML_GPM_METRIC_NVLINK_L12_TX" = 286
NVML_GPM_METRIC_NVLINK_L13_RX "NVML_GPM_METRIC_NVLINK_L13_RX" = 287
NVML_GPM_METRIC_NVLINK_L13_TX "NVML_GPM_METRIC_NVLINK_L13_TX" = 288
NVML_GPM_METRIC_NVLINK_L14_RX "NVML_GPM_METRIC_NVLINK_L14_RX" = 289
NVML_GPM_METRIC_NVLINK_L14_TX "NVML_GPM_METRIC_NVLINK_L14_TX" = 290
NVML_GPM_METRIC_NVLINK_L15_RX "NVML_GPM_METRIC_NVLINK_L15_RX" = 291
NVML_GPM_METRIC_NVLINK_L15_TX "NVML_GPM_METRIC_NVLINK_L15_TX" = 292
NVML_GPM_METRIC_NVLINK_L16_RX "NVML_GPM_METRIC_NVLINK_L16_RX" = 293
NVML_GPM_METRIC_NVLINK_L16_TX "NVML_GPM_METRIC_NVLINK_L16_TX" = 294
NVML_GPM_METRIC_NVLINK_L17_RX "NVML_GPM_METRIC_NVLINK_L17_RX" = 295
NVML_GPM_METRIC_NVLINK_L17_TX "NVML_GPM_METRIC_NVLINK_L17_TX" = 296
NVML_GPM_METRIC_MAX "NVML_GPM_METRIC_MAX" = 333
ctypedef enum nvmlPowerProfileType_t "nvmlPowerProfileType_t":
NVML_POWER_PROFILE_MAX_P "NVML_POWER_PROFILE_MAX_P" = 0
NVML_POWER_PROFILE_MAX_Q "NVML_POWER_PROFILE_MAX_Q" = 1
NVML_POWER_PROFILE_COMPUTE "NVML_POWER_PROFILE_COMPUTE" = 2
NVML_POWER_PROFILE_MEMORY_BOUND "NVML_POWER_PROFILE_MEMORY_BOUND" = 3
NVML_POWER_PROFILE_NETWORK "NVML_POWER_PROFILE_NETWORK" = 4
NVML_POWER_PROFILE_BALANCED "NVML_POWER_PROFILE_BALANCED" = 5
NVML_POWER_PROFILE_LLM_INFERENCE "NVML_POWER_PROFILE_LLM_INFERENCE" = 6
NVML_POWER_PROFILE_LLM_TRAINING "NVML_POWER_PROFILE_LLM_TRAINING" = 7
NVML_POWER_PROFILE_RBM "NVML_POWER_PROFILE_RBM" = 8
NVML_POWER_PROFILE_DCPCIE "NVML_POWER_PROFILE_DCPCIE" = 9
NVML_POWER_PROFILE_HMMA_SPARSE "NVML_POWER_PROFILE_HMMA_SPARSE" = 10
NVML_POWER_PROFILE_HMMA_DENSE "NVML_POWER_PROFILE_HMMA_DENSE" = 11
NVML_POWER_PROFILE_SYNC_BALANCED "NVML_POWER_PROFILE_SYNC_BALANCED" = 12
NVML_POWER_PROFILE_HPC "NVML_POWER_PROFILE_HPC" = 13
NVML_POWER_PROFILE_MIG "NVML_POWER_PROFILE_MIG" = 14
NVML_POWER_PROFILE_MAX "NVML_POWER_PROFILE_MAX" = 15
ctypedef enum nvmlDeviceAddressingModeType_t "nvmlDeviceAddressingModeType_t":
NVML_DEVICE_ADDRESSING_MODE_NONE "NVML_DEVICE_ADDRESSING_MODE_NONE" = 0
NVML_DEVICE_ADDRESSING_MODE_HMM "NVML_DEVICE_ADDRESSING_MODE_HMM" = 1
NVML_DEVICE_ADDRESSING_MODE_ATS "NVML_DEVICE_ADDRESSING_MODE_ATS" = 2
ctypedef enum nvmlPRMCounterId_t "nvmlPRMCounterId_t":
NVML_PRM_COUNTER_ID_NONE "NVML_PRM_COUNTER_ID_NONE" = 0
NVML_PRM_COUNTER_ID_PPCNT_PHYSICAL_LAYER_CTRS_LINK_DOWN_EVENTS "NVML_PRM_COUNTER_ID_PPCNT_PHYSICAL_LAYER_CTRS_LINK_DOWN_EVENTS" = 1
NVML_PRM_COUNTER_ID_PPCNT_PHYSICAL_LAYER_CTRS_SUCCESSFUL_RECOVERY_EVENTS "NVML_PRM_COUNTER_ID_PPCNT_PHYSICAL_LAYER_CTRS_SUCCESSFUL_RECOVERY_EVENTS" = 2
NVML_PRM_COUNTER_ID_PPCNT_RECOVERY_CTRS_TOTAL_SUCCESSFUL_RECOVERY_EVENTS "NVML_PRM_COUNTER_ID_PPCNT_RECOVERY_CTRS_TOTAL_SUCCESSFUL_RECOVERY_EVENTS" = 101
NVML_PRM_COUNTER_ID_PPCNT_RECOVERY_CTRS_TIME_SINCE_LAST_RECOVERY "NVML_PRM_COUNTER_ID_PPCNT_RECOVERY_CTRS_TIME_SINCE_LAST_RECOVERY" = 102
NVML_PRM_COUNTER_ID_PPCNT_RECOVERY_CTRS_TIME_BETWEEN_LAST_TWO_RECOVERIES "NVML_PRM_COUNTER_ID_PPCNT_RECOVERY_CTRS_TIME_BETWEEN_LAST_TWO_RECOVERIES" = 103
NVML_PRM_COUNTER_ID_PPCNT_PORTCOUNTERS_PORT_XMIT_WAIT "NVML_PRM_COUNTER_ID_PPCNT_PORTCOUNTERS_PORT_XMIT_WAIT" = 201
NVML_PRM_COUNTER_ID_PPCNT_PLR_RCV_CODES "NVML_PRM_COUNTER_ID_PPCNT_PLR_RCV_CODES" = 301
NVML_PRM_COUNTER_ID_PPCNT_PLR_RCV_CODE_ERR "NVML_PRM_COUNTER_ID_PPCNT_PLR_RCV_CODE_ERR" = 302
NVML_PRM_COUNTER_ID_PPCNT_PLR_RCV_UNCORRECTABLE_CODE "NVML_PRM_COUNTER_ID_PPCNT_PLR_RCV_UNCORRECTABLE_CODE" = 303
NVML_PRM_COUNTER_ID_PPCNT_PLR_XMIT_CODES "NVML_PRM_COUNTER_ID_PPCNT_PLR_XMIT_CODES" = 304
NVML_PRM_COUNTER_ID_PPCNT_PLR_XMIT_RETRY_CODES "NVML_PRM_COUNTER_ID_PPCNT_PLR_XMIT_RETRY_CODES" = 305
NVML_PRM_COUNTER_ID_PPCNT_PLR_XMIT_RETRY_EVENTS "NVML_PRM_COUNTER_ID_PPCNT_PLR_XMIT_RETRY_EVENTS" = 306
NVML_PRM_COUNTER_ID_PPCNT_PLR_SYNC_EVENTS "NVML_PRM_COUNTER_ID_PPCNT_PLR_SYNC_EVENTS" = 307
NVML_PRM_COUNTER_ID_PPRM_OPER_RECOVERY "NVML_PRM_COUNTER_ID_PPRM_OPER_RECOVERY" = 1001
ctypedef enum nvmlPowerProfileOperation_t "nvmlPowerProfileOperation_t":
NVML_POWER_PROFILE_OPERATION_CLEAR "NVML_POWER_PROFILE_OPERATION_CLEAR" = 0
NVML_POWER_PROFILE_OPERATION_SET "NVML_POWER_PROFILE_OPERATION_SET" = 1
NVML_POWER_PROFILE_OPERATION_SET_AND_OVERWRITE "NVML_POWER_PROFILE_OPERATION_SET_AND_OVERWRITE" = 2
NVML_POWER_PROFILE_OPERATION_MAX "NVML_POWER_PROFILE_OPERATION_MAX" = 3
# types
ctypedef struct nvmlPciInfoExt_v1_t 'nvmlPciInfoExt_v1_t':
unsigned int version
unsigned int domain
unsigned int bus
unsigned int device
unsigned int pciDeviceId
unsigned int pciSubSystemId
unsigned int baseClass
unsigned int subClass
char busId[32]
ctypedef struct nvmlCoolerInfo_v1_t 'nvmlCoolerInfo_v1_t':
unsigned int version
unsigned int index
nvmlCoolerControl_t signalType
nvmlCoolerTarget_t target
ctypedef struct nvmlDramEncryptionInfo_v1_t 'nvmlDramEncryptionInfo_v1_t':
unsigned int version
nvmlEnableState_t encryptionState
ctypedef struct nvmlMarginTemperature_v1_t 'nvmlMarginTemperature_v1_t':
unsigned int version
int marginTemperature
ctypedef struct nvmlClockOffset_v1_t 'nvmlClockOffset_v1_t':
unsigned int version
nvmlClockType_t type
nvmlPstates_t pstate
int clockOffsetMHz
int minClockOffsetMHz
int maxClockOffsetMHz
ctypedef struct nvmlFanSpeedInfo_v1_t 'nvmlFanSpeedInfo_v1_t':
unsigned int version
unsigned int fan
unsigned int speed
ctypedef struct nvmlDevicePerfModes_v1_t 'nvmlDevicePerfModes_v1_t':
unsigned int version
char str[2048]
ctypedef struct nvmlDeviceCurrentClockFreqs_v1_t 'nvmlDeviceCurrentClockFreqs_v1_t':
unsigned int version
char str[2048]
ctypedef struct nvmlEccSramErrorStatus_v1_t 'nvmlEccSramErrorStatus_v1_t':
unsigned int version
unsigned long long aggregateUncParity
unsigned long long aggregateUncSecDed
unsigned long long aggregateCor
unsigned long long volatileUncParity
unsigned long long volatileUncSecDed
unsigned long long volatileCor
unsigned long long aggregateUncBucketL2
unsigned long long aggregateUncBucketSm
unsigned long long aggregateUncBucketPcie
unsigned long long aggregateUncBucketMcu
unsigned long long aggregateUncBucketOther
unsigned int bThresholdExceeded
ctypedef struct nvmlPlatformInfo_v2_t 'nvmlPlatformInfo_v2_t':
unsigned int version
unsigned char ibGuid[16]
unsigned char chassisSerialNumber[16]
unsigned char slotNumber
unsigned char trayIndex
unsigned char hostId
unsigned char peerType
unsigned char moduleId
ctypedef unsigned int nvmlDeviceArchitecture_t 'nvmlDeviceArchitecture_t'
ctypedef unsigned int nvmlBusType_t 'nvmlBusType_t'
ctypedef unsigned int nvmlFanControlPolicy_t 'nvmlFanControlPolicy_t'
ctypedef unsigned int nvmlPowerSource_t 'nvmlPowerSource_t'
ctypedef unsigned char nvmlPowerScopeType_t 'nvmlPowerScopeType_t'
ctypedef unsigned int nvmlVgpuTypeId_t 'nvmlVgpuTypeId_t'
ctypedef unsigned int nvmlVgpuInstance_t 'nvmlVgpuInstance_t'
ctypedef struct nvmlVgpuHeterogeneousMode_v1_t 'nvmlVgpuHeterogeneousMode_v1_t':
unsigned int version
unsigned int mode
ctypedef struct nvmlVgpuPlacementId_v1_t 'nvmlVgpuPlacementId_v1_t':
unsigned int version
unsigned int placementId
ctypedef struct nvmlVgpuPlacementList_v2_t 'nvmlVgpuPlacementList_v2_t':
unsigned int version
unsigned int placementSize
unsigned int count
unsigned int* placementIds
unsigned int mode
ctypedef struct nvmlVgpuTypeBar1Info_v1_t 'nvmlVgpuTypeBar1Info_v1_t':
unsigned int version
unsigned long long bar1Size
ctypedef struct nvmlVgpuRuntimeState_v1_t 'nvmlVgpuRuntimeState_v1_t':
unsigned int version
unsigned long long size
ctypedef struct nvmlSystemConfComputeSettings_v1_t 'nvmlSystemConfComputeSettings_v1_t':
unsigned int version
unsigned int environment
unsigned int ccFeature
unsigned int devToolsMode
unsigned int multiGpuMode
ctypedef struct nvmlConfComputeSetKeyRotationThresholdInfo_v1_t 'nvmlConfComputeSetKeyRotationThresholdInfo_v1_t':
unsigned int version
unsigned long long maxAttackerAdvantage
ctypedef struct nvmlConfComputeGetKeyRotationThresholdInfo_v1_t 'nvmlConfComputeGetKeyRotationThresholdInfo_v1_t':
unsigned int version
unsigned long long attackerAdvantage
ctypedef unsigned char nvmlGpuFabricState_t 'nvmlGpuFabricState_t'
ctypedef struct nvmlSystemDriverBranchInfo_v1_t 'nvmlSystemDriverBranchInfo_v1_t':
unsigned int version
char branch[80]
ctypedef unsigned int nvmlAffinityScope_t 'nvmlAffinityScope_t'
ctypedef struct nvmlTemperature_v1_t 'nvmlTemperature_v1_t':
unsigned int version
nvmlTemperatureSensors_t sensorType
int temperature
ctypedef struct nvmlNvlinkSupportedBwModes_v1_t 'nvmlNvlinkSupportedBwModes_v1_t':
unsigned int version
unsigned char bwModes[23]
unsigned char totalBwModes
ctypedef struct nvmlNvlinkGetBwMode_v1_t 'nvmlNvlinkGetBwMode_v1_t':
unsigned int version
unsigned int bIsBest
unsigned char bwMode
ctypedef struct nvmlNvlinkSetBwMode_v1_t 'nvmlNvlinkSetBwMode_v1_t':
unsigned int version
unsigned int bSetBest
unsigned char bwMode
ctypedef struct nvmlDeviceCapabilities_v1_t 'nvmlDeviceCapabilities_v1_t':
unsigned int version
unsigned int capMask
ctypedef struct nvmlPowerSmoothingProfile_v1_t 'nvmlPowerSmoothingProfile_v1_t':
unsigned int version
unsigned int profileId
unsigned int paramId
double value
ctypedef struct nvmlPowerSmoothingState_v1_t 'nvmlPowerSmoothingState_v1_t':
unsigned int version
nvmlEnableState_t state
ctypedef struct nvmlDeviceAddressingMode_v1_t 'nvmlDeviceAddressingMode_v1_t':
unsigned int version
unsigned int value
ctypedef struct nvmlRepairStatus_v1_t 'nvmlRepairStatus_v1_t':
unsigned int version
unsigned int bChannelRepairPending
unsigned int bTpcRepairPending
ctypedef struct nvmlPdi_v1_t 'nvmlPdi_v1_t':
unsigned int version
unsigned long long value
ctypedef void* nvmlDevice_t 'nvmlDevice_t'
ctypedef void* nvmlGpuInstance_t 'nvmlGpuInstance_t'
ctypedef void* nvmlUnit_t 'nvmlUnit_t'
ctypedef void* nvmlEventSet_t 'nvmlEventSet_t'
ctypedef void* nvmlSystemEventSet_t 'nvmlSystemEventSet_t'
ctypedef void* nvmlComputeInstance_t 'nvmlComputeInstance_t'
ctypedef void* nvmlGpmSample_t 'nvmlGpmSample_t'
ctypedef struct nvmlPciInfo_t 'nvmlPciInfo_t':
char busIdLegacy[16]
unsigned int domain
unsigned int bus
unsigned int device
unsigned int pciDeviceId
unsigned int pciSubSystemId
char busId[32]
ctypedef struct nvmlEccErrorCounts_t 'nvmlEccErrorCounts_t':
unsigned long long l1Cache
unsigned long long l2Cache
unsigned long long deviceMemory
unsigned long long registerFile
ctypedef struct nvmlUtilization_t 'nvmlUtilization_t':
unsigned int gpu
unsigned int memory
ctypedef struct nvmlMemory_t 'nvmlMemory_t':
unsigned long long total
unsigned long long free
unsigned long long used
ctypedef struct nvmlMemory_v2_t 'nvmlMemory_v2_t':
unsigned int version
unsigned long long total
unsigned long long reserved
unsigned long long free
unsigned long long used
ctypedef struct nvmlBAR1Memory_t 'nvmlBAR1Memory_t':
unsigned long long bar1Total
unsigned long long bar1Free
unsigned long long bar1Used
ctypedef struct nvmlProcessInfo_v1_t 'nvmlProcessInfo_v1_t':
unsigned int pid
unsigned long long usedGpuMemory
ctypedef struct nvmlProcessInfo_v2_t 'nvmlProcessInfo_v2_t':
unsigned int pid
unsigned long long usedGpuMemory
unsigned int gpuInstanceId
unsigned int computeInstanceId
ctypedef struct nvmlProcessInfo_t 'nvmlProcessInfo_t':
unsigned int pid
unsigned long long usedGpuMemory
unsigned int gpuInstanceId
unsigned int computeInstanceId
ctypedef struct nvmlProcessDetail_v1_t 'nvmlProcessDetail_v1_t':
unsigned int pid
unsigned long long usedGpuMemory
unsigned int gpuInstanceId
unsigned int computeInstanceId
unsigned long long usedGpuCcProtectedMemory
ctypedef struct nvmlDeviceAttributes_t 'nvmlDeviceAttributes_t':
unsigned int multiprocessorCount
unsigned int sharedCopyEngineCount
unsigned int sharedDecoderCount
unsigned int sharedEncoderCount
unsigned int sharedJpegCount
unsigned int sharedOfaCount
unsigned int gpuInstanceSliceCount
unsigned int computeInstanceSliceCount
unsigned long long memorySizeMB
ctypedef struct nvmlC2cModeInfo_v1_t 'nvmlC2cModeInfo_v1_t':
unsigned int isC2cEnabled
ctypedef struct nvmlRowRemapperHistogramValues_t 'nvmlRowRemapperHistogramValues_t':
unsigned int max
unsigned int high
unsigned int partial