Commit dc93e82 changed start.c so that the 48M DFLL is now running open loop, rather than closed loop on systems with a crystal clock. Sadly, this makes 48M less accurate than it could be.
The referenced commit says only "fixed USB enumeration bug in bootloader and core", but the only change was to make the DFLL open loop in all cases. There is no other explanation.
Can we have closed loop mode back???
Why it matters:
Sadly, even with the crystal, it isn't possible to derive an exact 48kHz sample rate from the 48M clock. I2S requires a bit clock of 32 * sample rate, and the best divisor that ZeroI2S (or any code) can pick is 31, yielding a sample rate of 48M / 31 / 32 = 48,387Hz.
While this is still off from a desired sample rate:
a) it is within tolerance of DAC chips like Adafruit's own PCM510x based boards,
and b) it is a known sample rate, so my audio code can generate correct pitches knowing it.
When the 48M clock is open loop, the exact rate varies by board, and has been observed to be off enough to cause tones to be out of tune. It doesn't take much: 1 part in 1000 is enough to be out of tune, and I have observed this on Feather M4 Express boards.
Commit dc93e82 changed
start.cso that the 48M DFLL is now running open loop, rather than closed loop on systems with a crystal clock. Sadly, this makes 48M less accurate than it could be.The referenced commit says only "fixed USB enumeration bug in bootloader and core", but the only change was to make the DFLL open loop in all cases. There is no other explanation.
Can we have closed loop mode back???
Why it matters:
Sadly, even with the crystal, it isn't possible to derive an exact 48kHz sample rate from the 48M clock. I2S requires a bit clock of 32 * sample rate, and the best divisor that ZeroI2S (or any code) can pick is 31, yielding a sample rate of 48M / 31 / 32 = 48,387Hz.
While this is still off from a desired sample rate:
a) it is within tolerance of DAC chips like Adafruit's own PCM510x based boards,
and b) it is a known sample rate, so my audio code can generate correct pitches knowing it.
When the 48M clock is open loop, the exact rate varies by board, and has been observed to be off enough to cause tones to be out of tune. It doesn't take much: 1 part in 1000 is enough to be out of tune, and I have observed this on Feather M4 Express boards.