LiteX normally uses Wishbone bus. The CPU system in Zynq uses AXI to communicate them both you need to add an Wishbone <-> AXI bridge to the design.
This one is quite simple and can be easily integrated: https://github.com/wallento/wb2axi/blob/master/src/wb2axi.sv
LiteX normally uses Wishbone bus. The CPU system in Zynq uses AXI to communicate them both you need to add an Wishbone <-> AXI bridge to the design.
This one is quite simple and can be easily integrated: https://github.com/wallento/wb2axi/blob/master/src/wb2axi.sv