Fix some typos in paging section. (#128)

* Fix typo on line 201 of paging section

"page table" instead of "page teble"

* Update 03_Paging.md

Add a missing "it" in "if it is 0". 
Split the sentence into two parts, so that its easier to read.

* Update I_Acknowledgments.md

Author: frischerZucker

04_Memory_Management/03_Paging.md

@@ -198,7 +198,7 @@ Below is a list of all the fields present in the table entries, with an explanat
 * **User/Supervisor**: It describes the privilege level required to access this address. If clear the page has the supervisor level, while if it is set the level is user. The cpu identifies supervisor/user level by checking the CPL (current protection level, set by the segment registers). If it is less than 3 then the accesses are made in supervisor mode, if it's equal to 3 they are made in user mode.
 * **PWT** (Page Level Write Through): Controls the caching policy (write-through or write-back). I usually leave it to 0, for more information refer to the Intel Developer Manuals.
 * **PCD** (Page Level Cache Disable): Controls the caching of individual pages or tables. I usually leave it to 0, for more information refer to the Intel Developer Manuals.
-* **A** (Accessed): This value is set by the CPU, if is 0 it means the page hasn't been accessed yet. It's set when the page (or page teble) has been accessed since this bit was last cleared.
+* **A** (Accessed): This value is set by the CPU. If it is 0, it means the page hasn't been accessed yet. It's set when the page (or page table) has been accessed since this bit was last cleared.
 * **D** (Dirty): If set, indicates that a page has been written to since last cleared. This flag is supposed to only apply to page tables, but some emulators will set it on other levels as well. This flag and the accessed flag are provided for being use by the memory management software, the CPU only set it when its value is 0. Otherwise, is up to the operating system's memory manager to decide if it has to be cleared or not. Ignoring them is also fine.
 * **PS** (Page Size): Reserved in the pml4, if set on the PDPR it means address translation stops at this level and is mapping a 1GB page. Check for 1gb page support before using this. More commonly this can be set on the PD entry to stop translation at that level, and map a 2MB page.
 * **PAT** (Page Attribute Table Index) only for the page table: It selects the PAT entry (in combination with the PWT and PCD bits above), refer to the Intel Manual for a more detailed explanation.

99_Appendices/I_Acknowledgments.md

@@ -27,3 +27,4 @@ In no particular order:
 - @AntoninRuan ([https://github.com/AntoninRuan](https://github.com/AntoninRuan))
 - @sudw1n ([https://github.com/sudw1n](https://github.com/sudw1n))
 - @alexdev404 ([https://github.com/AlexDev404](https://github.com/AlexDev404))
+- @frischerZucker ([https://github.com/frischerZucker](https://github.com/frischerZucker))