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RISC-V64 arch. port support RVV Extension;
1 parent 0c92f48 commit edffa04

6 files changed

Lines changed: 386 additions & 4 deletions

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‎ports/risc-v64/gnu/inc/tx_port.h‎

Lines changed: 10 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -105,15 +105,23 @@ typedef unsigned short USHORT;
105105
thread creation is less than this value, the thread create call will return an error. */
106106

107107
#ifndef TX_MINIMUM_STACK
108-
#define TX_MINIMUM_STACK 1024 /* Minimum stack size for this port */
108+
#if defined(__riscv_vector)
109+
#define TX_MINIMUM_STACK (1024 + 16448) /* Minimum stack size for this port */
110+
#else
111+
#define TX_MINIMUM_STACK 1024 /* Minimum stack size for this port */
112+
#endif
109113
#endif
110114

111115

112116
/* Define the system timer thread's default stack size and priority. These are only applicable
113117
if TX_TIMER_PROCESS_IN_ISR is not defined. */
114118

115119
#ifndef TX_TIMER_THREAD_STACK_SIZE
116-
#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */
120+
#if defined(__riscv_vector)
121+
#define TX_TIMER_THREAD_STACK_SIZE (1024 + 16448) /* Default timer thread stack size */
122+
#else
123+
#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */
124+
#endif
117125
#endif
118126

119127
#ifndef TX_TIMER_THREAD_PRIORITY

‎ports/risc-v64/gnu/src/tx_thread_context_restore.S‎

Lines changed: 130 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -138,6 +138,36 @@ _tx_thread_context_restore:
138138
csrw fcsr, t0
139139
#endif
140140

141+
#if defined(__riscv_vector)
142+
/* Recover vector registers v0-v31 */
143+
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
144+
addi t1, sp, 64*8
145+
#else
146+
addi t1, sp, 31*8
147+
#endif
148+
addi t2, t1, 5*8
149+
vsetvli t3, zero, e8, m8, ta, ma
150+
vle8.v v0, (t2) // Recover v0 ~ v7
151+
add t2, t2, t3
152+
vle8.v v8, (t2) // Recover v8 ~ v15
153+
add t2, t2, t3
154+
vle8.v v16, (t2) // Recover v16 ~ v23
155+
add t2, t2, t3
156+
vle8.v v24, (t2) // Recover v24 ~ v31
157+
add t2, t2, t3
158+
159+
/* Recover vector CSRs */
160+
ld t2, 0*8(t1)
161+
ld t3, 1*8(t1)
162+
ld t4, 2*8(t1)
163+
vsetvl zero, t2, t3
164+
csrw vstart, t4
165+
ld t4, 3*8(t1)
166+
csrw vxsat, t4
167+
ld t4, 4*8(t1)
168+
csrw vxrm, t4
169+
#endif
170+
141171
/* Recover standard registers. */
142172

143173
/* Restore registers,
@@ -168,6 +198,10 @@ _tx_thread_context_restore:
168198
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
169199
li t0, 0x2000 // Set FS bits (bits 14:13 to 01) for FP state
170200
or t1, t1, t0
201+
#endif
202+
#if defined(__riscv_vector)
203+
li t0, 0x0200 // Set VS bits (bits 10:9 to 01) for vector state
204+
or t1, t1, t0
171205
#endif
172206
csrw mstatus, t1 // Update mstatus safely
173207

@@ -194,6 +228,21 @@ _tx_thread_context_restore:
194228
#else
195229
addi sp, sp, 32*8 // Recover stack frame - without floating point enabled
196230
#endif
231+
232+
#if defined(__riscv_vector)
233+
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
234+
addi t0, sp, -65*8
235+
#else
236+
addi t0, sp, -32*8
237+
#endif
238+
csrr t1, vlenb // Get vector register byte length
239+
slli t1, t1, 5 // Multiply by 32 (number of vector registers)
240+
addi t1, t1, 5*8 // Add vector CSR space: vl, vtype, vstart, vxrm, vxsat
241+
add sp, sp, t1 // Recover vector stack frame
242+
243+
ld t1, 18*8(t0) // Recover t1
244+
ld t0, 19*8(t0) // Recover t0
245+
#endif
197246
mret // Return to point of interrupt
198247

199248
/* } */
@@ -273,6 +322,36 @@ _tx_thread_no_preempt_restore:
273322
csrw fcsr, t0 // Restore fcsr
274323
#endif
275324

325+
#if defined(__riscv_vector)
326+
/* Recover vector registers v0-v31 */
327+
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
328+
addi t1, sp, 64*8
329+
#else
330+
addi t1, sp, 31*8
331+
#endif
332+
addi t2, t1, 5*8
333+
vsetvli t3, zero, e8, m8, ta, ma
334+
vle8.v v0, (t2) // Recover v0 ~ v7
335+
add t2, t2, t3
336+
vle8.v v8, (t2) // Recover v8 ~ v15
337+
add t2, t2, t3
338+
vle8.v v16, (t2) // Recover v16 ~ v23
339+
add t2, t2, t3
340+
vle8.v v24, (t2) // Recover v24 ~ v31
341+
add t2, t2, t3
342+
343+
/* Recover vector CSRs */
344+
ld t2, 0*8(t1)
345+
ld t3, 1*8(t1)
346+
ld t4, 2*8(t1)
347+
vsetvl zero, t2, t3
348+
csrw vstart, t4
349+
ld t4, 3*8(t1)
350+
csrw vxsat, t4
351+
ld t4, 4*8(t1)
352+
csrw vxrm, t4
353+
#endif
354+
276355
/* Recover the saved context and return to the point of interrupt. */
277356

278357
/* Recover standard registers. */
@@ -294,6 +373,10 @@ _tx_thread_no_preempt_restore:
294373
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
295374
li t0, 0x2000 // Set FS bits for FP state
296375
or t1, t1, t0
376+
#endif
377+
#if defined(__riscv_vector)
378+
li t0, 0x0200 // Set VS bits (bits 10:9 to 01) for vector state
379+
or t1, t1, t0
297380
#endif
298381
csrw mstatus, t1 // Update mstatus safely
299382

@@ -320,6 +403,21 @@ _tx_thread_no_preempt_restore:
320403
#else
321404
addi sp, sp, 32*8 // Recover stack frame - without floating point enabled
322405
#endif
406+
407+
#if defined(__riscv_vector)
408+
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
409+
addi t0, sp, -65*8
410+
#else
411+
addi t0, sp, -32*8
412+
#endif
413+
csrr t1, vlenb // Get vector register byte length
414+
slli t1, t1, 5 // Multiply by 32 (number of vector registers)
415+
addi t1, t1, 5*8 // Add vector CSR space: vl, vtype, vstart, vxrm, vxsat
416+
add sp, sp, t1 // Recover vector stack frame
417+
418+
ld t1, 18*8(t0) // Recover t1
419+
ld t0, 19*8(t0) // Recover t0
420+
#endif
323421
mret // Return to point of interrupt
324422

325423
/* }
@@ -362,6 +460,38 @@ _tx_thread_preempt_restore:
362460
fsd f27, 58*8(t0) // Store fs11
363461
#endif
364462

463+
#if defined(__riscv_vector)
464+
/* Store vector registers and CSRs */
465+
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
466+
addi t1, t0, 64*8
467+
#else
468+
addi t1, t0, 31*8
469+
#endif
470+
/* Store vector CSRs */
471+
csrr t2, vl // Store vl
472+
sd t2, 0*8(t1)
473+
csrr t2, vtype // Store vtype
474+
sd t2, 1*8(t1)
475+
csrr t2, vstart // Store vstart
476+
sd t2, 2*8(t1)
477+
csrr t2, vxrm // Store vxrm
478+
sd t2, 3*8(t1)
479+
csrr t2, vxsat // Store vxsat
480+
sd t2, 4*8(t1)
481+
482+
/* Store vector registers v0-v31 */
483+
addi t2, t1, 5*8
484+
vsetvli t3, zero, e8, m8, ta, ma
485+
vse8.v v0, 0(t2) // Store v0 ~ v7
486+
add t2, t2, t3
487+
vse8.v v8, 0(t2) // Store v8 ~ v15
488+
add t2, t2, t3
489+
vse8.v v16, 0(t2) // Store v16 ~ v23
490+
add t2, t2, t3
491+
vse8.v v24, 0(t2) // Store v24 ~ v31
492+
add t2, t2, t3
493+
#endif
494+
365495
/* Store standard preserved registers. */
366496

367497
sd x9, 11*8(t0) // Store s1

‎ports/risc-v64/gnu/src/tx_thread_context_save.S‎

Lines changed: 79 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -151,6 +151,38 @@ _tx_thread_context_save:
151151
sd t0, 63*8(sp) // Store fcsr
152152
#endif
153153

154+
#if defined(__riscv_vector)
155+
/* Store vector registers and CSRs */
156+
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
157+
addi t1, sp, 64*8
158+
#else
159+
addi t1, sp, 31*8
160+
#endif
161+
/* Store vector CSRs */
162+
csrr t2, vl // Store vl
163+
sd t2, 0*8(t1)
164+
csrr t2, vtype // Store vtype
165+
sd t2, 1*8(t1)
166+
csrr t2, vstart // Store vstart
167+
sd t2, 2*8(t1)
168+
csrr t2, vxrm // Store vxrm
169+
sd t2, 3*8(t1)
170+
csrr t2, vxsat // Store vxsat
171+
sd t2, 4*8(t1)
172+
173+
/* Store vector registers v0-v31 */
174+
addi t2, t1, 5*8
175+
vsetvli t3, zero, e8, m8, ta, ma
176+
vse8.v v0, 0(t2) // Store v0 ~ v7
177+
add t2, t2, t3
178+
vse8.v v8, 0(t2) // Store v8 ~ v15
179+
add t2, t2, t3
180+
vse8.v v16, 0(t2) // Store v16 ~ v23
181+
add t2, t2, t3
182+
vse8.v v24, 0(t2) // Store v24 ~ v31
183+
add t2, t2, t3
184+
#endif
185+
154186
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
155187
call _tx_execution_isr_enter // Call the ISR execution enter function
156188
#endif
@@ -241,6 +273,38 @@ _tx_thread_not_nested_save:
241273
sd t0, 63*8(sp) // Store fcsr
242274
#endif
243275

276+
#if defined(__riscv_vector)
277+
/* Store vector registers and CSRs */
278+
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
279+
addi t1, sp, 64*8
280+
#else
281+
addi t1, sp, 31*8
282+
#endif
283+
/* Store vector CSRs */
284+
csrr t2, vl // Store vl
285+
sd t2, 0*8(t1)
286+
csrr t2, vtype // Store vtype
287+
sd t2, 1*8(t1)
288+
csrr t2, vstart // Store vstart
289+
sd t2, 2*8(t1)
290+
csrr t2, vxrm // Store vxrm
291+
sd t2, 3*8(t1)
292+
csrr t2, vxsat // Store vxsat
293+
sd t2, 4*8(t1)
294+
295+
/* Store vector registers v0-v31 */
296+
addi t2, t1, 5*8
297+
vsetvli t3, zero, e8, m8, ta, ma
298+
vse8.v v0, 0(t2) // Store v0 ~ v7
299+
add t2, t2, t3
300+
vse8.v v8, 0(t2) // Store v8 ~ v15
301+
add t2, t2, t3
302+
vse8.v v16, 0(t2) // Store v16 ~ v23
303+
add t2, t2, t3
304+
vse8.v v24, 0(t2) // Store v24 ~ v31
305+
add t2, t2, t3
306+
#endif
307+
244308
/* Save the current stack pointer in the thread's control block. */
245309
/* _tx_thread_current_ptr -> tx_thread_stack_ptr = sp; */
246310

@@ -280,4 +344,19 @@ _tx_thread_idle_system_save:
280344
#else
281345
addi sp, sp, 32*8 // Recover the reserved stack space
282346
#endif
347+
348+
#if defined(__riscv_vector)
349+
#if defined(__riscv_float_abi_single) || defined(__riscv_float_abi_double)
350+
addi t0, sp, -65*8
351+
#else
352+
addi t0, sp, -32*8
353+
#endif
354+
csrr t1, vlenb // Get vector register byte length
355+
slli t1, t1, 5 // Multiply by 32 (number of vector registers)
356+
addi t1, t1, 5*8 // Add vector CSR space: vl, vtype, vstart, vxrm, vxsat
357+
add sp, sp, t1 // Recover vector stack frame
358+
359+
ld t1, 18*8(t0) // Recover t1
360+
ld t0, 19*8(t0) // Recover t0
361+
#endif
283362
ret // Return to calling ISR

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