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bivvyrkhuangtao
bivvy
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rkhuangtao
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drm/rockchip: vop: slit dither register field definitions
Change-Id: Id6fb68b88641839fa66c01eda980e07b4317b435 Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
1 parent 2bb9ec2 commit 09866a1

3 files changed

Lines changed: 45 additions & 30 deletions

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‎drivers/gpu/drm/rockchip/rockchip_drm_vop.c‎

Lines changed: 14 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -2357,32 +2357,34 @@ static void vop_update_csc(struct drm_crtc *crtc)
23572357

23582358
switch (s->bus_format) {
23592359
case MEDIA_BUS_FMT_RGB565_1X16:
2360-
val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB565);
2360+
VOP_CTRL_SET(vop, dither_down_en, 1);
2361+
VOP_CTRL_SET(vop, dither_down_mode, RGB888_TO_RGB565);
23612362
break;
23622363
case MEDIA_BUS_FMT_RGB666_1X18:
23632364
case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
2364-
val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB666);
2365+
VOP_CTRL_SET(vop, dither_down_en, 1);
2366+
VOP_CTRL_SET(vop, dither_down_mode, RGB888_TO_RGB666);
23652367
break;
23662368
case MEDIA_BUS_FMT_YUV8_1X24:
23672369
case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
2368-
val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(1);
2370+
VOP_CTRL_SET(vop, dither_down_en, 0);
2371+
VOP_CTRL_SET(vop, pre_dither_down_en, 1);
23692372
break;
23702373
case MEDIA_BUS_FMT_YUV10_1X30:
23712374
case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
2372-
val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0);
2375+
VOP_CTRL_SET(vop, dither_down_en, 0);
2376+
VOP_CTRL_SET(vop, pre_dither_down_en, 0);
23732377
break;
23742378
case MEDIA_BUS_FMT_RGB888_1X24:
23752379
default:
2376-
val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0);
2380+
VOP_CTRL_SET(vop, dither_down_en, 0);
2381+
VOP_CTRL_SET(vop, pre_dither_down_en, 0);
23772382
break;
23782383
}
23792384

2380-
if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA)
2381-
val |= PRE_DITHER_DOWN_EN(0);
2382-
else
2383-
val |= PRE_DITHER_DOWN_EN(1);
2384-
val |= DITHER_DOWN_MODE_SEL(DITHER_DOWN_ALLEGRO);
2385-
VOP_CTRL_SET(vop, dither_down, val);
2385+
VOP_CTRL_SET(vop, pre_dither_down_en,
2386+
s->output_mode == ROCKCHIP_OUT_MODE_AAAA ? 0 : 1);
2387+
VOP_CTRL_SET(vop, dither_down_sel, DITHER_DOWN_ALLEGRO);
23862388

23872389
VOP_CTRL_SET(vop, dclk_ddr,
23882390
s->output_mode == ROCKCHIP_OUT_MODE_YUV420 ? 1 : 0);
@@ -2539,7 +2541,7 @@ static void vop_crtc_enable(struct drm_crtc *crtc)
25392541
VOP_CTRL_SET(vop, hdmi_pin_pol, val);
25402542
VOP_CTRL_SET(vop, sw_genlock, 1);
25412543
VOP_CTRL_SET(vop, sw_uv_offset_en, 1);
2542-
VOP_CTRL_SET(vop, dither_up, 1);
2544+
VOP_CTRL_SET(vop, dither_up_en, 1);
25432545
break;
25442546
default:
25452547
DRM_ERROR("unsupport connector_type[%d]\n", s->output_type);

‎drivers/gpu/drm/rockchip/rockchip_drm_vop.h‎

Lines changed: 5 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -148,8 +148,11 @@ struct vop_ctrl {
148148
struct vop_reg mipi_pin_pol;
149149
struct vop_reg dp_dclk_pol;
150150
struct vop_reg dp_pin_pol;
151-
struct vop_reg dither_up;
152-
struct vop_reg dither_down;
151+
struct vop_reg dither_down_sel;
152+
struct vop_reg dither_down_mode;
153+
struct vop_reg dither_down_en;
154+
struct vop_reg pre_dither_down_en;
155+
struct vop_reg dither_up_en;
153156

154157
struct vop_reg sw_dac_sel;
155158
struct vop_reg tve_sw_mode;
@@ -593,11 +596,6 @@ enum dither_down_mode_sel {
593596
DITHER_DOWN_FRC = 0x1
594597
};
595598

596-
#define PRE_DITHER_DOWN_EN(x) ((x) << 0)
597-
#define DITHER_DOWN_EN(x) ((x) << 1)
598-
#define DITHER_DOWN_MODE(x) ((x) << 2)
599-
#define DITHER_DOWN_MODE_SEL(x) ((x) << 3)
600-
601599
enum vop_pol {
602600
HSYNC_POSITIVE = 0,
603601
VSYNC_POSITIVE = 1,

‎drivers/gpu/drm/rockchip/rockchip_vop_reg.c‎

Lines changed: 26 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -225,8 +225,11 @@ static const struct vop_ctrl rk3288_ctrl_data = {
225225
.mipi_dclk_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x1, 31, 3, 2, -1),
226226
.mipi_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x7, 28, 3, 2, -1),
227227

228-
.dither_down = VOP_REG(RK3288_DSP_CTRL1, 0xf, 1),
229-
.dither_up = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6),
228+
.dither_down_sel = VOP_REG(RK3288_DSP_CTRL1, 0x1, 4),
229+
.dither_down_mode = VOP_REG(RK3288_DSP_CTRL1, 0x1, 3),
230+
.dither_down_en = VOP_REG(RK3288_DSP_CTRL1, 0x1, 2),
231+
.pre_dither_down_en = VOP_REG(RK3288_DSP_CTRL1, 0x1, 1),
232+
.dither_up_en = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6),
230233

231234
.dsp_out_yuv = VOP_REG_VER(RK3399_POST_SCL_CTRL, 0x1, 2, 3, 5, -1),
232235
.dsp_data_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1f, 12),
@@ -925,8 +928,11 @@ static const struct vop_ctrl rk3328_ctrl_data = {
925928
.edp_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 27),
926929
.mipi_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 31),
927930

928-
.dither_down = VOP_REG(RK3328_DSP_CTRL1, 0xf, 1),
929-
.dither_up = VOP_REG(RK3328_DSP_CTRL1, 0x1, 6),
931+
.dither_down_sel = VOP_REG(RK3328_DSP_CTRL1, 0x1, 4),
932+
.dither_down_mode = VOP_REG(RK3328_DSP_CTRL1, 0x1, 3),
933+
.dither_down_en = VOP_REG(RK3328_DSP_CTRL1, 0x1, 2),
934+
.pre_dither_down_en = VOP_REG(RK3328_DSP_CTRL1, 0x1, 1),
935+
.dither_up_en = VOP_REG(RK3328_DSP_CTRL1, 0x1, 6),
930936

931937
.dsp_data_swap = VOP_REG(RK3328_DSP_CTRL0, 0x1f, 12),
932938
.dsp_ccir656_avg = VOP_REG(RK3328_DSP_CTRL0, 0x1, 20),
@@ -1104,7 +1110,10 @@ static const struct vop_ctrl rk3036_ctrl_data = {
11041110
.dsp_blank = VOP_REG(RK3036_DSP_CTRL1, 0x1, 24),
11051111
.dclk_pol = VOP_REG(RK3036_DSP_CTRL0, 0x1, 7),
11061112
.pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0x7, 4),
1107-
.dither_down = VOP_REG(RK3036_DSP_CTRL0, 0x3, 10),
1113+
.dither_down_sel = VOP_REG(RK3036_DSP_CTRL0, 0x1, 27),
1114+
.dither_down_en = VOP_REG(RK3036_DSP_CTRL0, 0x1, 11),
1115+
.dither_down_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 10),
1116+
.dither_up_en = VOP_REG(RK3036_DSP_CTRL0, 0x1, 9),
11081117
.dsp_layer_sel = VOP_REG(RK3036_DSP_CTRL0, 0x1, 8),
11091118
.htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
11101119
.hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0),
@@ -1339,8 +1348,10 @@ static const struct vop_ctrl rk3366_lit_ctrl_data = {
13391348
.lvds_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 17),
13401349
.hdmi_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 9),
13411350
.rgb_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 1),
1342-
.dither_up = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 2),
1343-
.dither_down = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x7, 6),
1351+
.dither_down_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 8),
1352+
.dither_down_sel = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 7),
1353+
.dither_down_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 6),
1354+
.dither_up_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 2),
13441355
.dsp_data_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1f, 9),
13451356
.dsp_ccir656_avg = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 5),
13461357
.dsp_black = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 15),
@@ -1440,8 +1451,10 @@ static const struct vop_ctrl px30_ctrl_data = {
14401451
.lvds_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 17),
14411452
.hdmi_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 9),
14421453
.rgb_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 1),
1443-
.dither_up = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 2),
1444-
.dither_down = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x7, 6),
1454+
.dither_down_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 8),
1455+
.dither_down_sel = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 7),
1456+
.dither_down_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 6),
1457+
.dither_up_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 2),
14451458
.dsp_data_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1f, 9),
14461459
.dsp_ccir656_avg = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 5),
14471460
.dsp_black = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 15),
@@ -1576,8 +1589,10 @@ static const struct vop_ctrl rk3308_ctrl_data = {
15761589
.rgb_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 0),
15771590
.rgb_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 2),
15781591
.rgb_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 1),
1579-
.dither_up = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 2),
1580-
.dither_down = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x7, 6),
1592+
.dither_down_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 8),
1593+
.dither_down_sel = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 7),
1594+
.dither_down_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 6),
1595+
.dither_up_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 2),
15811596
.dsp_data_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1f, 9),
15821597
.dsp_ccir656_avg = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 5),
15831598
.dsp_black = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 15),

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