TinyMat

"A 4x4 7-bit systolic array multiplier on FPGA, verified with a UVM-inspired Python testbench over UART (Basys3)."

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The Project

• An external matrix multiplication accelerator (systolic array) in SystemVerilog for Basys3 fpga
• UVC for the MAC unit with functonal coverage based verification (Reached 100% in 1.33 min and 163345 transactions)
• A Python driver that sends data via UART, triggers computation, and reads the result back as Python arrays
• A UVM-inspired testbench in Python that automatically generates test cases, runs them on the FPGA, and verifies the output against golden results generated by NumPy

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Folders

• matmul_acclerator (Vivado project folder)
  • Run the vivado file to directly open the proj
  • there is Bitstream file already generated that works on BASYS3 only
• Design file
  • All the .sv and constraint files seperately provided
  • mac_UVC
    • EDA Playground : https://edaplayground.com/x/ZJis
    • .sv files also avaliable for the UVC
    • Test bench achieve 100% functional coverage in 1.33 min and 163345 transactions
• Test_Bench.py
  • run this once the FPGA is ready and comports are connected
• fpga_frimware.py
  • import this into another ptoject to use the fpga for computation
• example_use.py
  • clean example to show you how it works

Since this is an active personal project it is only 4X4 matrix and only 8 bits for now I aim to impliment more complex protocol as I learn (internal: ABP, AHB, AXI as seems fit, External: I2C).
[] UART DMA

Tiny Demo

small_demo_video.mp4

Waveform example of one transaction

Example of Tx

Example of compute and Rx

Calculation

Given that the system runs at 100MHZ and 9600 Baud for UART One entire transaction takes 69.8ms to from when the transmit starts to compute and write back. 1/69.8ms $\approx$ 14 Transfer/s

Overall TB

Systollic array UVC