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LeilaCY-Linquinchou77
LeilaCY-Lin
authored and
quinchou77
committed
fwk: refactor UCSI port and PD port map
Some project's pd port order is different, we need to switch the port order for UCSI. Refactor UCSI port and PD port map for the further project. BRANCH=fwk-main BUG=https://app.clickup.com/t/86eqhvxm6 TEST= use console cmd "cypdctl ucsi 1" enable UCSI log and check port is match on marigold unit. Signed-off-by: LeilaCY-Lin <LeilaCY_Lin@compal.com> (cherry picked from commit 64c85ed)
1 parent e5376e2 commit ddb55ab

4 files changed

Lines changed: 79 additions & 23 deletions

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‎zephyr/program/framework/CMakeLists.txt‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -59,6 +59,7 @@ if(DEFINED CONFIG_BOARD_LOTUS)
5959
"lotus/src/gpu_configuration.c"
6060
"lotus/src/gpu_f75303.c"
6161
"src/usbc_4port_config.c"
62+
"src/ucsi_port_13_16.c"
6263
"src/temperature_filter.c"
6364
)
6465
zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_AMD_STT
@@ -72,6 +73,7 @@ if(DEFINED CONFIG_BOARD_AZALEA)
7273
zephyr_include_directories("include/azalea")
7374
zephyr_library_sources(
7475
"src/battery_13.c"
76+
"src/ucsi_port_13_16.c"
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"azalea/src/charger.c"
7678
"azalea/src/cpu_power.c"
7779
"azalea/src/input_module.c"
@@ -91,6 +93,7 @@ if(DEFINED CONFIG_BOARD_MARIGOLD)
9193
zephyr_include_directories("include/marigold")
9294
zephyr_library_sources(
9395
"src/battery_13.c"
96+
"src/ucsi_port_13_16.c"
9497
"marigold/src/charger.c"
9598
"marigold/src/cpu_power.c"
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"marigold/src/power_sequence.c"

‎zephyr/program/framework/include/ucsi.h‎

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Original file line numberDiff line numberDiff line change
@@ -8,6 +8,7 @@
88
#ifndef __CROS_EC_UCSI_H
99
#define __CROS_EC_UCSI_H
1010

11+
#include "common.h"
1112

1213
/************************************************/
1314
/* UCSI CONTROL DEFINITION */
@@ -44,6 +45,21 @@ enum ucsi_command {
4445
UCSI_CMD_GET_PD_MESSAGE
4546
};
4647

48+
/**
49+
* PD chip indicates to the UCSI change connector, only return 1(port0)/2(port1)
50+
*/
51+
enum pd_chip_ucsi_connector {
52+
PD_CHIP_UCSI_CONNECTOR_1 = 1,
53+
PD_CHIP_UCSI_CONNECTOR_2,
54+
};
55+
56+
struct ucsi_to_pd_port_map {
57+
int pd_controller;
58+
int pd_controller_port;
59+
};
60+
61+
extern struct ucsi_to_pd_port_map ucsi_pd_port_map[];
62+
4763
int ucsi_write_tunnel(void);
4864
int ucsi_read_tunnel(int controller);
4965
int ucsi_startup(int controller);

‎zephyr/program/framework/src/ucsi.c‎

Lines changed: 33 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -35,6 +35,7 @@
3535
static int ucsi_debug_enable;
3636
static uint8_t s0ix_connector_change_indicator;
3737
static bool read_complete;
38+
static int pd_ucsi_port_map[PD_PORT_COUNT];
3839

3940
void ucsi_set_debug(bool enable)
4041
{
@@ -85,7 +86,7 @@ int ucsi_write_tunnel(void)
8586
uint8_t *message_out = host_get_memmap(EC_CUSTOMIZED_MEMMAP_UCSI_MESSAGE_OUT);
8687
uint8_t *command = host_get_memmap(EC_CUSTOMIZED_MEMMAP_UCSI_COMMAND);
8788
uint8_t change_connector_indicator = 0;
88-
int i;
89+
int controller;
8990
int offset = 0;
9091
int rv = EC_SUCCESS;
9192

@@ -100,7 +101,7 @@ int ucsi_write_tunnel(void)
100101
CPRINTS("UCSI PPM_RESET");
101102
}
102103

103-
for (i = 0; i < PD_CHIP_COUNT; i++)
104+
for (int i = 0; i < PD_CHIP_COUNT; i++)
104105
pd_chip_ucsi_info[i].read_tunnel_complete = 0;
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106107
switch (*command) {
@@ -131,24 +132,19 @@ int ucsi_write_tunnel(void)
131132
change_connector_indicator =
132133
*host_get_memmap(EC_CUSTOMIZED_MEMMAP_UCSI_CTR_SPECIFIC + offset) & 0x7f;
133134

134-
if (change_connector_indicator > 0x02) {
135-
/*
136-
* Port 3 (b011) should be controller 1 UCSI port 1
137-
* Port 4 (b100) should be controller 1 UCSI port 2
138-
*/
135+
if (change_connector_indicator > 0 && change_connector_indicator !=
136+
ucsi_pd_port_map[change_connector_indicator-1].pd_controller_port) {
139137
*host_get_memmap(EC_CUSTOMIZED_MEMMAP_UCSI_CTR_SPECIFIC + offset) =
140-
((*host_get_memmap(EC_CUSTOMIZED_MEMMAP_UCSI_CTR_SPECIFIC + offset)
141-
& 0x80) | (change_connector_indicator >> 1));
142-
i = 1;
143-
} else
144-
i = 0;
138+
ucsi_pd_port_map[change_connector_indicator-1].pd_controller_port;
139+
}
140+
controller = ucsi_pd_port_map[change_connector_indicator-1].pd_controller;
145141

146-
pd_chip_ucsi_info[i].wait_ack = 1;
147-
rv = cypd_write_reg_block(i, CCG_MESSAGE_OUT_REG, message_out, 16);
148-
rv = cypd_write_reg_block(i, CCG_CONTROL_REG, command, 8);
142+
pd_chip_ucsi_info[controller].wait_ack = 1;
143+
rv = cypd_write_reg_block(controller, CCG_MESSAGE_OUT_REG, message_out, 16);
144+
rv = cypd_write_reg_block(controller, CCG_CONTROL_REG, command, 8);
149145
break;
150146
default:
151-
for (i = 0; i < PD_CHIP_COUNT; i++) {
147+
for (int i = 0; i < PD_CHIP_COUNT; i++) {
152148

153149
/**
154150
* If the controller does not needs to respond ACK,
@@ -314,13 +310,11 @@ int ucsi_read_tunnel(int controller)
314310
if (rv != EC_SUCCESS)
315311
CPRINTS("CCI_REG failed");
316312
/* we need to offset the pd connector number to correct number */
317-
if (controller == 1 && (pd_chip_ucsi_info[controller].cci & 0xFE))
318-
/*
319-
* Port 3 (b011) should be controller 1 UCSI port 1 (b001)
320-
* Port 4 (b100) should be controller 1 UCSI port 2 (b010)
321-
* CCI connector change indicate offset bit 1, so need to add 0x04 (0x2 << 1)
322-
*/
323-
pd_chip_ucsi_info[controller].cci += 0x04;
313+
if (pd_chip_ucsi_info[controller].cci & 0xFE) {
314+
pd_chip_ucsi_info[controller].cci = (pd_chip_ucsi_info[controller].cci & 0xFFFFFF01)
315+
| (pd_ucsi_port_map[controller*2+((pd_chip_ucsi_info[controller].cci & 0xFE)>>1)-1]
316+
<< 1);
317+
}
324318

325319
/* If data length is non zero, then get data */
326320
if (pd_chip_ucsi_info[controller].cci & 0xFF00) {
@@ -554,3 +548,19 @@ void check_ucsi_event_from_host(void)
554548
host_set_single_event(EC_HOST_EVENT_UCSI);
555549
}
556550
}
551+
552+
/**
553+
* Map the UCSI port to the PD port, so that we can use the PD port_id
554+
* to find the UCSI port number
555+
*/
556+
static void ucsi_pd_port_mapping(void)
557+
{
558+
int port_idx;
559+
560+
for (int i = 0; i < PD_PORT_COUNT; i++) {
561+
port_idx = (ucsi_pd_port_map[i].pd_controller * 2) +
562+
ucsi_pd_port_map[i].pd_controller_port;
563+
pd_ucsi_port_map[port_idx-1] = i+1;
564+
}
565+
}
566+
DECLARE_HOOK(HOOK_INIT, ucsi_pd_port_mapping, HOOK_PRIO_DEFAULT);

‎zephyr/program/framework/src/ucsi_port_13_16.c‎

Lines changed: 27 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,27 @@
1+
/*
2+
* Copyright 2024 The Chromium OS Authors. All rights reserved.
3+
* Use of this source code is governed by a BSD-style license that can be
4+
* found in the LICENSE file.
5+
*/
6+
7+
#include "ucsi.h"
8+
#include "cypress_pd_common.h"
9+
10+
enum ucsi_port {
11+
UCSI_PORT_1,
12+
UCSI_PORT_2,
13+
UCSI_PORT_3,
14+
UCSI_PORT_4,
15+
};
16+
17+
struct ucsi_to_pd_port_map ucsi_pd_port_map[] = {
18+
[UCSI_PORT_1] = {.pd_controller = PD_CHIP_0,
19+
.pd_controller_port = PD_CHIP_UCSI_CONNECTOR_1},
20+
[UCSI_PORT_2] = {.pd_controller = PD_CHIP_0,
21+
.pd_controller_port = PD_CHIP_UCSI_CONNECTOR_2},
22+
[UCSI_PORT_3] = {.pd_controller = PD_CHIP_1,
23+
.pd_controller_port = PD_CHIP_UCSI_CONNECTOR_1},
24+
[UCSI_PORT_4] = {.pd_controller = PD_CHIP_1,
25+
.pd_controller_port = PD_CHIP_UCSI_CONNECTOR_2},
26+
};
27+
BUILD_ASSERT(ARRAY_SIZE(ucsi_pd_port_map) == CONFIG_USB_PD_PORT_MAX_COUNT);

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