[24.04_linux-nvidia-6.17-next] ats always on v4 by nirmoy · Pull Request #424 · NVIDIA/NV-Kernels

nirmoy · 2026-05-15T16:05:58Z

BugLink: https://bugs.launchpad.net/bugs/2150727

Replicate the ATS always-on v4 stack from #401 for the 6.17 HWE branch.

This replaces the older ATS always-on support with the v4 CXL.cache, pre-CXL/CX10, and arm-smmu-v3 handling.

Validation:

patchscan upstream/24.04_linux-nvidia-6.17-next..HEAD origin linux --no-update: pass
validate-pr upstream/24.04_linux-nvidia-6.17-next..HEAD origin linux --no-update --base-branch 24.04_linux-nvidia-6.17-next: pass
git diff --check upstream/24.04_linux-nvidia-6.17-next..HEAD: pass
git log --check upstream/24.04_linux-nvidia-6.17-next..HEAD: pass

BugLink: https://bugs.launchpad.net/bugs/2150727 This reverts commit 11d6b22. Signed-off-by: Nirmoy Das <nirmoyd@nvidia.com>

… NVIDIA GPUs" BugLink: https://bugs.launchpad.net/bugs/2150727 This reverts commit 208b48c. Signed-off-by: Nirmoy Das <nirmoyd@nvidia.com>

…he capable devices" BugLink: https://bugs.launchpad.net/bugs/2150727 This reverts commit 967f9fe. Signed-off-by: Nirmoy Das <nirmoyd@nvidia.com>

…le devices BugLink: https://bugs.launchpad.net/bugs/2150727 Controlled by the IOMMU driver, ATS is usually enabled "on demand" when a given PASID on a device is attached to an I/O page table. This is working even when a device has no translation on its RID (i.e., the RID is IOMMU bypassed). However, certain PCIe devices require non-PASID ATS on their RID even when the RID is IOMMU bypassed. Call this "always on". For example, CXL spec r4.0 notes in sec 3.2.5.13 Memory Type on CXL.cache: "To source requests on CXL.cache, devices need to get the Host Physical Address (HPA) from the Host by means of an ATS request on CXL.io." In other words, the CXL.cache capability requires ATS; otherwise, it can't access host physical memory. Introduce a new pci_ats_always_on() helper for the IOMMU driver to scan a PCI device and shift ATS policies between "on demand" and "always on". Add the support for CXL.cache devices first. Pre-CXL devices will be added in quirks.c file. Note that pci_ats_always_on() validates against pci_ats_supported(), so we ensure that untrusted devices (e.g. external ports) will not be always on. This maintains the existing ATS security policy regarding potential side- channel attacks via ATS. Cc: linux-cxl@vger.kernel.org Suggested-by: Vikram Sethi <vsethi@nvidia.com> Suggested-by: Jason Gunthorpe <jgg@nvidia.com> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Reviewed-by: Jason Gunthorpe <jgg@nvidia.com> Reviewed-by: Kevin Tian <kevin.tian@intel.com> Tested-by: Nirmoy Das <nirmoyd@nvidia.com> Acked-by: Nirmoy Das <nirmoyd@nvidia.com> Signed-off-by: Nicolin Chen <nicolinc@nvidia.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> (backported from https://lore.kernel.org/r/f6734b9dad0050138676f11ecd14e9db1cf6b697.1777269009.git.nicolinc@nvidia.com) [Nirmoy: Adapt to already existing PCI_DVSEC_CXL_CACHE_CAPABLE.] Signed-off-by: Nirmoy Das <nirmoyd@nvidia.com>

BugLink: https://bugs.launchpad.net/bugs/2150727 Some NVIDIA GPU/NIC devices, though they don't implement CXL config space, have many CXL-like properties. Call this kind "pre-CXL". Similar to CXL.cache capability, these pre-CXL devices also require the ATS function even when their RIDs are IOMMU bypassed, i.e. keep ATS "always on" v.s. "on demand" when a non-zero PASID line gets enabled in SVA use cases. Introduce pci_dev_specific_ats_always_on() quirk function to scan a list of IDs for these devices. Then, include it in pci_ats_always_on(). Suggested-by: Jason Gunthorpe <jgg@nvidia.com> Reviewed-by: Nirmoy Das <nirmoyd@nvidia.com> Tested-by: Nirmoy Das <nirmoyd@nvidia.com> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Reviewed-by: Jason Gunthorpe <jgg@nvidia.com> Reviewed-by: Kevin Tian <kevin.tian@intel.com> Signed-off-by: Nicolin Chen <nicolinc@nvidia.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> (backported from https://lore.kernel.org/r/1a8cf5e88051ab5c10417edb94df598ecbc810cf.1777269009.git.nicolinc@nvidia.com) [Nirmoy: Apply after reverting older ATS always-on PCI quirk support.] Signed-off-by: Nirmoy Das <nirmoyd@nvidia.com>

BugLink: https://bugs.launchpad.net/bugs/2150727 When a device's default substream attaches to an identity domain, the SMMU driver currently sets the device's STE between two modes: Mode 1: Cfg=Translate, S1DSS=Bypass, EATS=1 Mode 2: Cfg=bypass (EATS is ignored by HW) When there is an active PASID (non-default substream), mode 1 is used. And when there is no PASID support or no active PASID, mode 2 is used. The driver will also downgrade an STE from mode 1 to mode 2, when the last active substream becomes inactive. However, there are PCIe devices that demand ATS to be always on. For these devices, their STEs have to use the mode 1 as HW ignores EATS with mode 2. Change the driver accordingly: - always use the mode 1 - never downgrade to mode 2 - allocate and retain a CD table (see note below) Note that these devices might not support PASID, i.e. doing non-PASID ATS. In such a case, the ssid_bits is set to 0. However, s1cdmax must be set to a !0 value in order to keep the S1DSS field effective. Thus, when a master requires ats_always_on, set its s1cdmax to at least 1, meaning that the CD table will have a dummy entry (SSID=1) that will never be used. Now for these devices, arm_smmu_cdtab_allocated() will always return true, v.s. false prior to this change. When its default substream is attached to an IDENTITY domain, its first CD is NULL in the table, which is a totally valid case. Thus, add "!master->ats_always_on" to the condition. Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Tested-by: Nirmoy Das <nirmoyd@nvidia.com> Acked-by: Nirmoy Das <nirmoyd@nvidia.com> Reviewed-by: Jason Gunthorpe <jgg@nvidia.com> Reviewed-by: Kevin Tian <kevin.tian@intel.com> Signed-off-by: Nicolin Chen <nicolinc@nvidia.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> (backported from https://lore.kernel.org/r/7403163ebf59380f88c7503b3adf0dae07428df8.1777269009.git.nicolinc@nvidia.com) [Nirmoy: Apply after reverting older ATS always-on arm-smmu-v3 support.] Signed-off-by: Nirmoy Das <nirmoyd@nvidia.com>

github-actions · 2026-05-15T16:16:32Z

PR Validation Report

Patchscan ✅ No Missing Fixes

All cherry-picked commits checked — no missing upstream fixes found.

PR Lint ✅ All checks passed

Details

Checking 6 commits...

Cherry-pick digest:
┌──────────────┬──────────────────────────────────────────────────────────────────┬────────────┬─────────┬───────────────────────────┐
│ Local        │ Referenced upstream / Patch subject                              │ Patch-ID   │ Subject │ SoB chain                 │
├──────────────┼──────────────────────────────────────────────────────────────────┼────────────┼─────────┼───────────────────────────┤
│ 4be3ced311d9 │ iommu/arm-smmu-v3: allow ats to be always on                     │ noted      │ found   │ ok, backporter: nirmoyd   │
├──────────────┼──────────────────────────────────────────────────────────────────┼────────────┼─────────┼───────────────────────────┤
│ a45a18d5d663 │ pci: allow ats to be always on for pre-cxl devices               │ noted      │ found   │ ok, backporter: nirmoyd   │
├──────────────┼──────────────────────────────────────────────────────────────────┼────────────┼─────────┼───────────────────────────┤
│ 7c934b82df29 │ pci: allow ats to be always on for cxl.cache capable devices     │ noted      │ found   │ ok, backporter: nirmoyd   │
├──────────────┼──────────────────────────────────────────────────────────────────┼────────────┼─────────┼───────────────────────────┤
│ 8a14dc9460f6 │ [Revert] pci: allow ats to be always on for cxl.cache capable de │ N/A        │ N/A     │ nirmoyd                   │
├──────────────┼──────────────────────────────────────────────────────────────────┼────────────┼─────────┼───────────────────────────┤
│ aabf8e6b87c8 │ [Revert] pci: allow ats to be always on for non-cxl nvidia gpus  │ N/A        │ N/A     │ nirmoyd                   │
├──────────────┼──────────────────────────────────────────────────────────────────┼────────────┼─────────┼───────────────────────────┤
│ 2c9944e391aa │ [Revert] iommu/arm-smmu-v3: allow ats to be always on            │ N/A        │ N/A     │ nirmoyd                   │
└──────────────┴──────────────────────────────────────────────────────────────────┴────────────┴─────────┴───────────────────────────┘

Lint: all checks passed.

nirmoy · 2026-05-17T16:19:00Z

Boro review

Latest watcher review: open review

Head: 8f9eaa3f3139

This comment is maintained by nv-pr-bot. It is updated when the GitHub watcher publishes a newer review.

nirmoy · 2026-05-18T15:39:42Z

Validated on nvidia@10.105.57.17.

Result: PASS for the PR424 GPU ATS path.

Evidence:

PR head: 8f9eaa3f3139f (nirmoy:codex/ats-always-on-v4-6.17)
Booted kernel: 6.17.13-pr424test
Test build used local-only debug marker commit 2b68bc94df101 for dmesg provenance
0002:81:00.0: PR424 marker logged with cache_capable=1; ATSCtl: Enable+
0002:c1:00.0: PR424 marker logged with cache_capable=1; ATSCtl: Enable+
nvidia-smi works with driver 600.09
nvidia/600.09 DKMS installed for 6.17.13-pr424test
CUDA DVS smoke passed: sanity-uvm-ats_malloc_host, sanity-uvm-texture_simple, sanity-cudaLaunchKernel

Note: dmesg still has one F_TRANSLATION event from 0002:e1:00.0, but that is the embedded Renesas USB controller, not either NVIDIA GPU.

nvmochs · 2026-05-18T15:56:47Z

@nirmoy No issues or concerns with the code changes in this PR, but why are our acks and Brad's SOB present in these commits?

clsotog · 2026-05-18T16:03:25Z

I was going to ask the same as Matt like why there is acks there?

nirmoy · 2026-05-18T16:11:27Z

ah codex cherry-picked patches from the bos kernel. Let me remove those

nirmoy · 2026-05-18T16:14:26Z

Removed the inherited BOS Acked-by trailers and Brad’s Signed-off-by from the six commits; range-diff is message-only and code is unchanged.

clsotog

Acked-by: Carol L Soto <csoto@nvidia.com>

nvmochs · 2026-05-18T17:08:49Z

Removed the inherited BOS Acked-by trailers and Brad’s Signed-off-by from the six commits; range-diff is message-only and code is unchanged.

Thanks Nirmoy!

Acked-by: Matthew R. Ochs <mochs@nvidia.com>

jamieNguyenNVIDIA · 2026-05-18T21:04:53Z

Acked-by: Jamie Nguyen <jamien@nvidia.com>

nvmochs · 2026-05-19T15:14:28Z

Merged, closing PR.

13a3a0e2c9f2 (nnoble/nvidia-6.17-next) NVIDIA: VR: SAUCE: iommu/arm-smmu-v3: Allow ATS to be always on
6d9a85f08edd NVIDIA: VR: SAUCE: PCI: Allow ATS to be always on for pre-CXL devices
30467c81e93d NVIDIA: VR: SAUCE: PCI: Allow ATS to be always on for CXL.cache capable devices
9a8761c61f3e Revert "NVIDIA: VR: SAUCE: PCI: Allow ATS to be always on for CXL.cache capable devices"
40dfc9e38bcb Revert "NVIDIA: VR: SAUCE: PCI: Allow ATS to be always on for non-CXL NVIDIA GPUs"
11ad64dea3f5 Revert "NVIDIA: VR: SAUCE: iommu/arm-smmu-v3: Allow ATS to be always on"

nirmoy and others added 6 commits May 15, 2026 09:04

Revert "NVIDIA: VR: SAUCE: iommu/arm-smmu-v3: Allow ATS to be always on"

2c9944e

BugLink: https://bugs.launchpad.net/bugs/2150727 This reverts commit 11d6b22. Signed-off-by: Nirmoy Das <nirmoyd@nvidia.com>

Revert "NVIDIA: VR: SAUCE: PCI: Allow ATS to be always on for non-CXL…

aabf8e6

… NVIDIA GPUs" BugLink: https://bugs.launchpad.net/bugs/2150727 This reverts commit 208b48c. Signed-off-by: Nirmoy Das <nirmoyd@nvidia.com>

Revert "NVIDIA: VR: SAUCE: PCI: Allow ATS to be always on for CXL.cac…

8a14dc9

…he capable devices" BugLink: https://bugs.launchpad.net/bugs/2150727 This reverts commit 967f9fe. Signed-off-by: Nirmoy Das <nirmoyd@nvidia.com>

nirmoy marked this pull request as draft May 15, 2026 16:07

nirmoy marked this pull request as ready for review May 18, 2026 15:40

nirmoy force-pushed the codex/ats-always-on-v4-6.17 branch from 8f9eaa3 to 4be3ced Compare May 18, 2026 16:14

clsotog approved these changes May 18, 2026

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nvmochs closed this May 19, 2026

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[24.04_linux-nvidia-6.17-next] ats always on v4#424

[24.04_linux-nvidia-6.17-next] ats always on v4#424
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