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Draft: RISC-V preprocessor#40

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fleurvanl wants to merge 8 commits intomainfrom
feature/risc-v-preprocesser
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Draft: RISC-V preprocessor#40
fleurvanl wants to merge 8 commits intomainfrom
feature/risc-v-preprocesser

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@fleurvanl fleurvanl marked this pull request as draft May 1, 2026 13:50
@fleurvanl fleurvanl marked this pull request as ready for review May 7, 2026 08:04
@ranieri
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ranieri commented May 7, 2026

We're still missing immediate value bucketing/normalization. That can go in a later pull request.



def test_parse_single_operand():
assert riscv.parse_instruction('j x032') == ('j', ('x032',))
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is "x032" a typo?

I would expect 0x32 (address) or x31 (register, but it only goes up to x31, there is no x32).

import re
from collections.abc import Iterator

from networkx import DiGraph
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This dependency is getting removed soon. We are standardizing on dict/list.

assert tokens.count('OBFUSCATED') == 2


# todo: adjust to risc-v; requires a riscv subfolder under asmtransformers/models
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This is a tokenizer thing, not a preprocessor thing, I'm OK with dropping this from here. It will be lifted from the ARM64 impl when we start generalizing.

"torch",
"transformers",
"tzlocal>=5.3.1",
"pandas>=3.0.2",
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Do we need this? Who's using it?

Also, it's not in the PDM lock change. If we really want to make sure everyone gets it, we need to re-lock.

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2 participants