[WIP] Wishbone config

[kabrodzki]

With the help of @piotr-binkowski I managed to configure the fastvdma to use the Wishbone bus.
What still we can change is the type of the reader and writer frontends - do we want to use the WishboneClassic* or do we want WishboneClassicPipelined*.

[piotr-binkowski]

I think that you should use WishboneClassic* interfaces as that is what LiteX seems to use internally. btw. You might want to check mixed configuration ie. CSRs accessed via Wishbone but LiteDRAM accessed via AXI (reader, writer or both) as that should offer significantly better performance.