[top,sw/dv] Clk pwr rst smoke tests

hw/top_chip/dv/top_chip_sim_cfg.hjson

@@ -194,6 +194,48 @@
       run_opts: ["+ChipMemSRAM_image_file={run_dir}/rom_ctrl_smoketest_cheri_sram.vmem",
                  "+ChipMemROM_image_file={proj_root}/sw/device/tests/rom_ctrl/mem_init_file.vmem"]
     }
+    {
+      name: rstmgr_smoke
+      uvm_test_seq: top_chip_dv_base_vseq
+      sw_images: ["rstmgr_smoketest_vanilla_sram:5" "bootrom:5"]
+      run_opts: ["+ChipMemSRAM_image_file={run_dir}/rstmgr_smoketest_vanilla_sram.vmem",
+                 "+ChipMemROM_image_file={run_dir}/bootrom.vmem"]
+    }
+    {
+      name: rstmgr_smoke_cheri
+      uvm_test_seq: top_chip_dv_base_vseq
+      sw_images: ["rstmgr_smoketest_cheri_sram:5" "bootrom:5"]
+      run_opts: ["+ChipMemSRAM_image_file={run_dir}/rstmgr_smoketest_cheri_sram.vmem",
+                 "+ChipMemROM_image_file={run_dir}/bootrom.vmem"]
+    }
+    {
+      name: clkmgr_smoke
+      uvm_test_seq: top_chip_dv_base_vseq
+      sw_images: ["clkmgr_smoketest_vanilla_sram:5" "bootrom:5"]
+      run_opts: ["+ChipMemSRAM_image_file={run_dir}/clkmgr_smoketest_vanilla_sram.vmem",
+                 "+ChipMemROM_image_file={run_dir}/bootrom.vmem"]
+    }
+    {
+      name: clkmgr_smoke_cheri
+      uvm_test_seq: top_chip_dv_base_vseq
+      sw_images: ["clkmgr_smoketest_cheri_sram:5" "bootrom:5"]
+      run_opts: ["+ChipMemSRAM_image_file={run_dir}/clkmgr_smoketest_cheri_sram.vmem",
+                 "+ChipMemROM_image_file={run_dir}/bootrom.vmem"]
+    }
+    {
+      name: pwrmgr_smoke
+      uvm_test_seq: top_chip_dv_base_vseq
+      sw_images: ["pwrmgr_smoketest_vanilla_sram:5" "bootrom:5"]
+      run_opts: ["+ChipMemSRAM_image_file={run_dir}/pwrmgr_smoketest_vanilla_sram.vmem",
+                 "+ChipMemROM_image_file={run_dir}/bootrom.vmem"]
+    }
+    {
+      name: pwrmgr_smoke_cheri
+      uvm_test_seq: top_chip_dv_base_vseq
+      sw_images: ["pwrmgr_smoketest_cheri_sram:5" "bootrom:5"]
+      run_opts: ["+ChipMemSRAM_image_file={run_dir}/pwrmgr_smoketest_cheri_sram.vmem",
+                 "+ChipMemROM_image_file={run_dir}/bootrom.vmem"]
+    }
     {
       name: rv_dm_ndm_reset_req
       uvm_test_seq: "top_chip_dv_rv_dm_ndm_reset_req_vseq"
@@ -297,6 +339,12 @@
         "axi_sram_smoke_cheri",
         "rom_ctrl_smoke",
         "rom_ctrl_smoke_cheri",
+        "rstmgr_smoke",
+        "rstmgr_smoke_cheri",
+        "clkmgr_smoke",
+        "clkmgr_smoke_cheri",
+        "pwrmgr_smoke",
+        "pwrmgr_smoke_cheri",
       ]
     }
     {
@@ -358,6 +406,27 @@
         "rom_ctrl_smoke_cheri"
       ]
     }
+    {
+      name: rstmgr
+      tests: [
+        "rstmgr_smoke",
+        "rstmgr_smoke_cheri"
+      ]
+    }
+    {
+      name: clkmgr
+      tests: [
+        "clkmgr_smoke",
+        "clkmgr_smoke_cheri"
+      ]
+    }
+    {
+      name: pwrmgr
+      tests: [
+        "pwrmgr_smoke",
+        "pwrmgr_smoke_cheri"
+      ]
+    }
     {
       name: rv_dm
       tests: [

sw/device/lib/hal/CMakeLists.txt

@@ -2,6 +2,6 @@
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 
-set(SRCS clkmgr.c ethernet.c gpio.c i2c.c mailbox.c mocha.c plic.c rom_ctrl.c rstmgr.c spi_device.c spi_host.c timer.c uart.c)
+set(SRCS clkmgr.c ethernet.c gpio.c i2c.c mailbox.c mocha.c plic.c pwrmgr.c rom_ctrl.c rstmgr.c spi_device.c spi_host.c timer.c uart.c)
 
 mocha_add_library(NAME hal LIBRARIES SOURCES ${SRCS})

sw/device/lib/hal/clkmgr.c

@@ -5,4 +5,49 @@
 #include "hal/clkmgr.h"
 #include "hal/mmio.h"
 #include <stdbool.h>
+#include <stddef.h>
 #include <stdint.h>
+
+bool clkmgr_gateable_clock_get_enabled(clkmgr_t clkmgr, size_t clock)
+{
+    if (clock != CLKMGR_GATEABLE_CLOCK_IO_PERI) {
+        return false;
+    }
+    return VOLATILE_READ(clkmgr->clk_enables).clk_io_peri_en;
+}
+
+void clkmgr_gateable_clock_set_enabled(clkmgr_t clkmgr, size_t clock, bool enabled)
+{
+    if (clock != CLKMGR_GATEABLE_CLOCK_IO_PERI) {
+        return;
+    }
+    clkmgr_clk_enables clk_enables = VOLATILE_READ(clkmgr->clk_enables);
+    clk_enables.clk_io_peri_en = enabled;
+    VOLATILE_WRITE(clkmgr->clk_enables, clk_enables);
+}
+
+bool clkmgr_hintable_clock_get_hint(clkmgr_t clkmgr, size_t clock)
+{
+    if (clock != CLKMGR_HINTABLE_CLOCK_MAIN) {
+        return false;
+    }
+    return VOLATILE_READ(clkmgr->clk_hints).clk_main_hint_hint;
+}
+
+void clkmgr_hintable_clock_set_hint(clkmgr_t clkmgr, size_t clock, bool enabled)
+{
+    if (clock != CLKMGR_HINTABLE_CLOCK_MAIN) {
+        return;
+    }
+    clkmgr_clk_hints clk_hints = VOLATILE_READ(clkmgr->clk_hints);
+    clk_hints.clk_main_hint_hint = enabled;
+    VOLATILE_WRITE(clkmgr->clk_hints, clk_hints);
+}
+
+bool clkmgr_hintable_clock_get_enabled(clkmgr_t clkmgr, size_t clock)
+{
+    if (clock != CLKMGR_HINTABLE_CLOCK_MAIN) {
+        return false;
+    }
+    return VOLATILE_READ(clkmgr->clk_hints_status).clk_main_hint_val;
+}

sw/device/lib/hal/clkmgr.h

@@ -4,13 +4,19 @@
 
 #pragma once
 
+#include "autogen/clkmgr.h"
 #include <stdbool.h>
+#include <stddef.h>
 #include <stdint.h>
 
-#define CLKMGR_ALERT_TEST_REG  (0x00)
-#define CLKMGR_CLK_ENABLES_REG (0x18)
-#define CLKMGR_CLK_ENABLES_ALL (1)
-
-typedef void *clkmgr_t;
+#define CLKMGR_GATEABLE_CLOCK_IO_PERI (0u)
+#define CLKMGR_HINTABLE_CLOCK_MAIN    (0u)
 
 #define CLKMGR_FROM_BASE_ADDR(addr) ((clkmgr_t)(addr))
+
+bool clkmgr_gateable_clock_get_enabled(clkmgr_t clkmgr, size_t clock);
+void clkmgr_gateable_clock_set_enabled(clkmgr_t clkmgr, size_t clock, bool enabled);
+
+bool clkmgr_hintable_clock_get_hint(clkmgr_t clkmgr, size_t clock);
+void clkmgr_hintable_clock_set_hint(clkmgr_t clkmgr, size_t clock, bool enabled);
+bool clkmgr_hintable_clock_get_enabled(clkmgr_t clkmgr, size_t clock);

sw/device/lib/hal/mocha.c

@@ -18,6 +18,7 @@ static const uintptr_t ethernet_base = 0x30000000ul;
 static const uintptr_t gpio_base = 0x40000000ul;
 static const uintptr_t clkmgr_base = 0x40020000ul;
 static const uintptr_t rstmgr_base = 0x40030000ul;
+static const uintptr_t pwrmgr_base = 0x40040000ul;
 static const uintptr_t rom_ctrl_base = 0x40050000ul;
 static const uintptr_t uart_base = 0x41000000ul;
 static const uintptr_t i2c_base = 0x42000000ul;
@@ -85,7 +86,7 @@ gpio_t mocha_system_gpio(void)
 clkmgr_t mocha_system_clkmgr(void)
 {
 #if defined(__riscv_zcherihybrid)
-    return (clkmgr_t)create_mmio_capability(clkmgr_base, 0x38u);
+    return (clkmgr_t)create_mmio_capability(clkmgr_base, sizeof(struct clkmgr_memory_layout));
 #else /* !defined(__riscv_zcherihybrid) */
     return (clkmgr_t)clkmgr_base;
 #endif /* defined(__riscv_zcherihybrid) */
@@ -100,6 +101,15 @@ rstmgr_t mocha_system_rstmgr(void)
 #endif /* defined(__riscv_zcherihybrid) */
 }
 
+pwrmgr_t mocha_system_pwrmgr(void)
+{
+#if defined(__riscv_zcherihybrid)
+    return (pwrmgr_t)create_mmio_capability(pwrmgr_base, 0x44u);
+#else /* !defined(__riscv_zcherihybrid) */
+    return (pwrmgr_t)pwrmgr_base;
+#endif /* defined(__riscv_zcherihybrid) */
+}
+
 rom_ctrl_t mocha_system_rom_ctrl(void)
 {
 #if defined(__riscv_zcherihybrid)

sw/device/lib/hal/mocha.h

@@ -12,6 +12,7 @@
 #include "hal/i2c.h"
 #include "hal/mailbox.h"
 #include "hal/plic.h"
+#include "hal/pwrmgr.h"
 #include "hal/rom_ctrl.h"
 #include "hal/rstmgr.h"
 #include "hal/spi_device.h"
@@ -38,6 +39,7 @@ ethernet_t mocha_system_ethernet(void);
 gpio_t mocha_system_gpio(void);
 clkmgr_t mocha_system_clkmgr(void);
 rstmgr_t mocha_system_rstmgr(void);
+pwrmgr_t mocha_system_pwrmgr(void);
 rom_ctrl_t mocha_system_rom_ctrl(void);
 uart_t mocha_system_uart(void);
 i2c_t mocha_system_i2c(void);

sw/device/lib/hal/pwrmgr.c

@@ -0,0 +1,59 @@
+// Copyright lowRISC contributors (COSMIC project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+#include "hal/pwrmgr.h"
+#include "hal/mmio.h"
+#include <stdint.h>
+
+uint32_t pwrmgr_control_get(pwrmgr_t pwrmgr)
+{
+    return DEV_READ(pwrmgr + PWRMGR_CONTROL_REG);
+}
+
+void pwrmgr_control_set(pwrmgr_t pwrmgr, uint32_t value)
+{
+    DEV_WRITE(pwrmgr + PWRMGR_CONTROL_REG, value & PWRMGR_CONTROL_MASK);
+}
+
+void pwrmgr_cfg_sync(pwrmgr_t pwrmgr)
+{
+    DEV_WRITE(pwrmgr + PWRMGR_CFG_CDC_SYNC_REG, 1u);
+    while ((DEV_READ(pwrmgr + PWRMGR_CFG_CDC_SYNC_REG) & 1u) != 0u) {
+    }
+}
+
+uint32_t pwrmgr_wakeup_enable_get(pwrmgr_t pwrmgr)
+{
+    return DEV_READ(pwrmgr + PWRMGR_WAKEUP_EN_REG);
+}
+
+void pwrmgr_wakeup_enable_set(pwrmgr_t pwrmgr, uint32_t value)
+{
+    DEV_WRITE(pwrmgr + PWRMGR_WAKEUP_EN_REG, value);
+}
+
+uint32_t pwrmgr_wakeup_status_get(pwrmgr_t pwrmgr)
+{
+    return DEV_READ(pwrmgr + PWRMGR_WAKE_STATUS_REG);
+}
+
+uint32_t pwrmgr_reset_status_get(pwrmgr_t pwrmgr)
+{
+    return DEV_READ(pwrmgr + PWRMGR_RESET_STATUS_REG);
+}
+
+uint32_t pwrmgr_escalate_reset_status_get(pwrmgr_t pwrmgr)
+{
+    return DEV_READ(pwrmgr + PWRMGR_ESCALATE_RESET_STATUS_REG);
+}
+
+uint32_t pwrmgr_wake_info_get(pwrmgr_t pwrmgr)
+{
+    return DEV_READ(pwrmgr + PWRMGR_WAKE_INFO_REG);
+}
+
+void pwrmgr_wake_info_clear(pwrmgr_t pwrmgr, uint32_t mask)
+{
+    DEV_WRITE(pwrmgr + PWRMGR_WAKE_INFO_REG, mask);
+}

sw/device/lib/hal/pwrmgr.h

@@ -0,0 +1,50 @@
+// Copyright lowRISC contributors (COSMIC project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// Power manager interface.
+
+#pragma once
+
+#include <stdint.h>
+
+#define PWRMGR_CONTROL_REG               (0x14)
+#define PWRMGR_CFG_CDC_SYNC_REG          (0x18)
+#define PWRMGR_WAKEUP_EN_REG             (0x20)
+#define PWRMGR_WAKE_STATUS_REG           (0x24)
+#define PWRMGR_RESET_STATUS_REG          (0x30)
+#define PWRMGR_ESCALATE_RESET_STATUS_REG (0x34)
+#define PWRMGR_WAKE_INFO_REG             (0x3C)
+
+#define PWRMGR_CONTROL_LOW_POWER_HINT_BIT (1u << 0)
+#define PWRMGR_CONTROL_CORE_CLK_EN_BIT    (1u << 4)
+#define PWRMGR_CONTROL_IO_CLK_EN_BIT      (1u << 5)
+#define PWRMGR_CONTROL_MAIN_PD_N_BIT      (1u << 6)
+#define PWRMGR_CONTROL_MASK \
+    (PWRMGR_CONTROL_LOW_POWER_HINT_BIT | PWRMGR_CONTROL_CORE_CLK_EN_BIT | \
+     PWRMGR_CONTROL_IO_CLK_EN_BIT | PWRMGR_CONTROL_MAIN_PD_N_BIT)
+
+#define PWRMGR_WAKEUP_EN_SOC_PROXY_EXT_WKUP_REQ_BIT (1u << 0)
+
+#define PWRMGR_WAKE_INFO_REASONS_BIT      (1u << 0)
+#define PWRMGR_WAKE_INFO_FALL_THROUGH_BIT (1u << 1)
+#define PWRMGR_WAKE_INFO_ABORT_BIT        (1u << 2)
+
+typedef void *pwrmgr_t;
+
+#define PWRMGR_FROM_BASE_ADDR(addr) ((pwrmgr_t)(addr))
+
+uint32_t pwrmgr_control_get(pwrmgr_t pwrmgr);
+void pwrmgr_control_set(pwrmgr_t pwrmgr, uint32_t value);
+
+void pwrmgr_cfg_sync(pwrmgr_t pwrmgr);
+
+uint32_t pwrmgr_wakeup_enable_get(pwrmgr_t pwrmgr);
+void pwrmgr_wakeup_enable_set(pwrmgr_t pwrmgr, uint32_t value);
+
+uint32_t pwrmgr_wakeup_status_get(pwrmgr_t pwrmgr);
+uint32_t pwrmgr_reset_status_get(pwrmgr_t pwrmgr);
+uint32_t pwrmgr_escalate_reset_status_get(pwrmgr_t pwrmgr);
+
+uint32_t pwrmgr_wake_info_get(pwrmgr_t pwrmgr);
+void pwrmgr_wake_info_clear(pwrmgr_t pwrmgr, uint32_t mask);

sw/device/lib/hal/rstmgr.c

@@ -4,19 +4,28 @@
 
 #include "hal/rstmgr.h"
 #include "hal/mmio.h"
-#include "hal/mocha.h"
 #include <stdint.h>
 
+uint32_t rstmgr_reset_reason_get(rstmgr_t rstmgr)
+{
+    return DEV_READ(rstmgr + RSTMGR_RESET_INFO_REG);
+}
+
+void rstmgr_reset_reason_clear(rstmgr_t rstmgr, uint32_t reason)
+{
+    DEV_WRITE(rstmgr + RSTMGR_RESET_INFO_REG, reason);
+}
+
 void rstmgr_software_reset_request(rstmgr_t rstmgr)
 {
     DEV_WRITE(rstmgr + RSTMGR_RESET_REQ_REG, RSTMGR_RESET_REQ_TRUE);
 }
 
 bool rstmgr_software_reset_info_get(rstmgr_t rstmgr)
 {
-    if (DEV_READ(rstmgr + RSTMGR_RESET_INFO_REG) & RSTMGR_RESET_INFO_SW_RESET) {
+    if (rstmgr_reset_reason_get(rstmgr) & RSTMGR_RESET_INFO_SW_RESET) {
         // Clear the info bit before returning.
-        DEV_WRITE(rstmgr + RSTMGR_RESET_INFO_REG, RSTMGR_RESET_INFO_SW_RESET);
+        rstmgr_reset_reason_clear(rstmgr, RSTMGR_RESET_INFO_SW_RESET);
         return true;
     }
     return false;

sw/device/lib/hal/rstmgr.h

@@ -12,11 +12,16 @@
 #define RSTMGR_RESET_REQ_REG       (0x4)
 #define RSTMGR_RESET_REQ_TRUE      (kMultiBitBool4True)
 #define RSTMGR_RESET_INFO_REG      (0x8)
+#define RSTMGR_RESET_INFO_POR      (0x1)
+#define RSTMGR_RESET_INFO_LOW_PWR  (0x2)
 #define RSTMGR_RESET_INFO_SW_RESET (0x4)
 
 typedef void *rstmgr_t;
 
 #define RSTMGR_FROM_BASE_ADDR(addr) ((rstmgr_t)(addr))
 
+uint32_t rstmgr_reset_reason_get(rstmgr_t rstmgr);
+void rstmgr_reset_reason_clear(rstmgr_t rstmgr, uint32_t reason);
+
 void rstmgr_software_reset_request(rstmgr_t rstmgr);
 bool rstmgr_software_reset_info_get(rstmgr_t rstmgr);

sw/device/tests/CMakeLists.txt

@@ -10,14 +10,16 @@ mocha_add_test(NAME axi_sram_smoketest SOURCES axi_sram/smoketest.c LIBRARIES ${
 mocha_add_test(NAME axi_sram_tag_test SOURCES axi_sram/tag_test.c LIBRARIES ${LIBS})
 # Cannot run this on verilator as the ethernet MAC is not in the verilator top
 mocha_add_test(NAME ethernet_smoketest SOURCES ethernet/smoketest.c LIBRARIES ${LIBS} SKIP_VERILATOR)
+mocha_add_test(NAME clkmgr_smoketest SOURCES clkmgr/smoketest.c LIBRARIES ${LIBS})
 mocha_add_test(NAME gpio_reg_access_test SOURCES gpio/reg_access_test.c LIBRARIES ${LIBS})
 # Can't run this test on FPGA or verilator tops and this test thinks that the GPIO inputs can be
 # driven externally
 mocha_add_test(NAME gpio_smoketest SOURCES gpio/smoketest.c LIBRARIES ${LIBS} SKIP_VERILATOR SKIP_FPGA)
 mocha_add_test(NAME i2c_smoketest SOURCES i2c/smoketest.c LIBRARIES ${LIBS})
 mocha_add_test(NAME mailbox_smoketest SOURCES mailbox/smoketest.c LIBRARIES ${LIBS})
 mocha_add_test(NAME plic_smoketest SOURCES plic/smoketest.c LIBRARIES ${LIBS})
-mocha_add_test(NAME rstmgr_software_reset SOURCES rstmgr/software_reset.c LIBRARIES ${LIBS})
+mocha_add_test(NAME pwrmgr_smoketest SOURCES pwrmgr/smoketest.c LIBRARIES ${LIBS})
+mocha_add_test(NAME rstmgr_smoketest SOURCES rstmgr/smoketest.c LIBRARIES ${LIBS})
 mocha_add_test(NAME spi_device_smoketest SOURCES spi_device/smoketest.c LIBRARIES ${LIBS})
 mocha_add_test(NAME spi_host_smoketest SOURCES spi_host/smoketest.c LIBRARIES ${LIBS})
 mocha_add_test(NAME tag_controller_smoketest SOURCES tag_controller/smoketest.c LIBRARIES ${LIBS})