5-Stage Pipelined ARM Processor Design

Course: CIE 439: Computer Architecture and Assembly Language
Institution: University of Science and Technology in Zewail City
Date: December 30, 2025

📌 Project Overview

This project involves the design, implementation, and verification of a 32-bit Pipelined ARM Processor using Verilog HDL. The processor is designed to execute a subset of the ARM instruction set architecture (ISA) and features a 5-stage pipeline (Fetch, Decode, Execute, Memory, Writeback) optimized for throughput.

A key focus of this implementation is the handling of Pipeline Hazards (Data and Control) through a dedicated Hazard Unit and Forwarding logic, as well as the support for Conditional Execution unique to the ARM architecture.

🎯 Key Features

• Pipelined Datapath: 5-stage architecture to increase instruction throughput compared to single-cycle implementations.
• Hazard Management:
  • Hazard Unit: Detects dependencies and inserts bubbles (stalls) or flushes the pipeline when necessary.
  • Forwarding Unit: Solves Read-After-Write (RAW) data hazards by forwarding results from the ALU or Memory stage directly to the Execute stage, minimizing stalls.
• Conditional Execution: Support for ARM condition codes (e.g., EQ, NE, LT), allowing instructions to execute only if specific flag criteria are met.
• Modular Design: Components include ALU, Register File, Control Unit, Extend Unit, and Pipeline Registers.

⚙️ Implementation Details

The system is implemented in Verilog and structured into distinct functional blocks:

1. Utility Modules: Multiplexers, Flops, and basic logic gates.
2. Register File & Extender: Handles 32-bit register storage and immediate value extension.
3. Execution Logic: ALU and conditional logic (Flag updating).
4. Control Unit: Main decoder and ALU decoder.
5. Hazard Unit: Logic to control Stall and Flush signals.

🧪 Verification & Testing

The processor was validated using a custom assembly test program (test_program.asm) designed to trigger specific architectural edge cases:

• Arithmetic Operations: ADD, SUB, AND, ORR.
• Flag Setting: SUBS instruction to update N, Z, C, V flags.
• Conditional Execution: ADDLT (Add if Less Than) to test predicate logic.
• Hazard Stress Test: Consecutive instructions with data dependencies to verify forwarding paths.

Success Condition: The testbench monitors the memory write port. The simulation is considered successful if the value 10 is written to address 100.

// From testbench output
if( dataadr === 100 & writedata === 10) begin
    $display (" Simulation succeeded ") ;
    $stop ;
end