feat(safety): Phase 1 — --safety-bounds umbrella + RV32 software bounds + RV32 div trap + safety-manifest.json#115
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feat(safety): Phase 1 — --safety-bounds umbrella + RV32 software bounds + RV32 div trap + safety-manifest.json#115avrabe wants to merge 1 commit into
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…ds + RV32 div trap + safety-manifest.json Implements Phase 1 of docs/binary-safety-design.md (#110). * CLI: new `--safety-bounds <mpu|software|mask|none>` flag. Keeps `--bounds-check` as a deprecated alias mapping to `--safety-bounds software`; emits a one-line deprecation notice. * CompileConfig grows a `safety_bounds: SafetyBounds` field; the ARM and RISC-V backends both read it. * Plumb through `BoundsCheckConfig` (now `SafetyBounds` at the public boundary). Existing `None` / `Software` semantics preserved on ARM. * RV32 selector: ported the software bounds-check sequence (`bgeu addr, mem_size, trap_label; ...; trap_label: ebreak`) to every i32 load/store and sub-word variant. * RV32 selector: emit `bne rs2, x0, ok; ebreak; ok: div` (and `divu`, `rem`, `remu`) trap-on-zero guards. Mirrors the existing ARM pattern (instruction_selector.rs:3895). * `safety-manifest.json` written alongside the output ELF whenever any safety flag is enabled. Schema: synth_version, target_triple, safety_bounds, safety_div_zero, safety_div_overflow, linear_memory_bytes. ## Hand-tested * `synth compile examples/wat/simple_add.wat --safety-bounds mpu -o /tmp/sa.elf --cortex-m` succeeds; `/tmp/sa.safety-manifest.json` contains the expected fields. * `synth compile examples/wat/simple_add.wat --bounds-check -o /tmp/sa.elf --cortex-m` prints the deprecation notice and still produces a working ELF. * `synth compile /tmp/rv_div.wat --backend riscv --target riscv32imac --safety-bounds software --all-exports -o /tmp/rv_div.elf` succeeds; RV32 ELF contains the div-by-zero trap sequence; manifest emitted. ## Out of scope (later phases per docs/binary-safety-design.md §6) * Phase 2: stack overflow (MSPLIM/PSPLIM/canary), CFI BTI/PAC * Phase 3: linear-memory poisoning * Phase 4: component-model type confusion * Phase 5: parameterise Compilation.v by SafetyProfile in Rocq ## Verification * `cargo test --workspace --exclude synth-verify` — all pass (z3-sys download blocked in this environment; synth-verify excluded accordingly, CI will exercise it). * `cargo clippy --workspace --exclude synth-verify --all-targets -- -D warnings` — clean. * `cargo fmt --check` — clean. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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Implements Phase 1 of the binary-safety roadmap landed in #110.
What's new
--safety-bounds <mpu|software|mask|none>flag.--bounds-checkremains as a deprecated alias mapping to--safety-bounds softwareand prints a one-line deprecation notice.safety-manifest.jsonalongside every emitted ELF when any safety flag is enabled. Schema:synth_version,target_triple,safety_bounds,safety_div_zero,safety_div_overflow,linear_memory_bytes. Verifiers/disasm tools can consume this.bgeu addr, mem_size, trap_labelpattern to every i32 load/store + sub-word variant in the RISC-V selector.bne rs2, x0, ok; ebreak; ok: div(and divu/rem/remu) — mirrors ARM's trap pattern. Closes the RV32 div-by-zero gap noted in docs: binary safety checks design — ARM + RISC-V opt-in safety profiles #110 §2.Hand-tested
Scope respected per design doc
Verification
cargo test --workspace --exclude synth-verify— all pass (z3-sys download was blocked locally; synth-verify excluded accordingly. CI will exercise the full workspace.)cargo clippy --workspace --exclude synth-verify --all-targets -- -D warnings— cleancargo fmt --check— clean🤖 Generated with Claude Code