feat(riscv): i64 Phase 1 — typed vstack + i64 arith/logic/compares/loads/stores#119
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feat(riscv): i64 Phase 1 — typed vstack + i64 arith/logic/compares/loads/stores#119avrabe wants to merge 1 commit into
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…mpares / loads / stores Refactors the RV32IMAC selector's virtual stack from `Vec<Reg>` to a typed `Vec<VstackVal>` enum so i64 values can live on the stack as a `(lo, hi)` register pair. RV32 doesn't require consecutive pairs (unlike ARM's LDRD/STRD), so any two distinct temps work. New typed helpers replace the untyped `push_val`/`pop_val`/`pop_pair`: push_i32 / push_i64 / pop_i32 / pop_i64 / pop_pair_i32 / pop_pair_i64 A new `SelectorError::StackTypeMismatch` variant surfaces selector-internal type bugs (rather than silently mixing halves). Phase 1 i64 ops implemented (selector-only — encoder already supports every base instruction needed): I64Const two emit_load_imm sequences (lo + hi) I64Add add lo, sltu carry, add hi, add hi+carry I64Sub sltu borrow, sub lo, sub hi, sub hi-borrow I64And/Or/Xor pairwise on lo and hi I64Eq / I64Ne xor diffs, or them, then sltiu/sltu → i32 0/1 I64Eqz or halves, sltiu → i32 0/1 I64ExtendI32U hi = 0 I64ExtendI32S hi = srai src, 31 I32WrapI64 zero-instruction; lo continues as i32 I64Load lw lo @offset, lw hi @offset+4 I64Store sw lo @offset, sw hi @offset+4 The return epilogue now handles both i32 (a0) and i64 (a0=lo, a1=hi) return values, matching the RV32 psABI for 64-bit returns. Out of scope (Phase 2): i64 mul/div/rem (runtime helpers), i64 shifts / rotates / clz / ctz / popcnt (shamt branching at 32-bit boundary), i64 ordered compares (lt/le/gt/ge S+U — hi-then-lo ladder), i64 sign- extending sub-word loads, I64Extend{8,16,32}S, sub-word i64 stores. These remain at the existing `_ => Unsupported` arm and error cleanly. Validation: - cargo test --package synth-backend-riscv: 98 → 110 passing (+12 new) - cargo clippy --package synth-backend-riscv -- -D warnings: clean - cargo fmt --check: clean - cargo build --workspace: clean Co-Authored-By: Claude Opus 4.7 <noreply@anthropic.com>
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Summary
Phase 1 of i64 support in the RV32IMAC backend. Refactors the selector's vstack from `Vec<Reg>` to a typed `Vec<VstackVal>` enum (`I32(Reg)` / `I64 { lo, hi }`), then layers in i64 arithmetic, logic, comparisons, conversions, and memory ops on top.
Bundled with #116 (RV32 Call leaf-subset) this brings the RV32 surface much closer to ARM-side parity.
What's in
Refactor (no behavior change for existing i32 paths)
New i64 ops
Epilogue now handles i64 returns via the RV psABI `(a0=lo, a1=hi)` convention.
What's out (deferred to Phase 2)
These ops still fall through to `SelectorError::Unsupported` — they fail loudly, no silent miscompilation:
Validation
Tests added
One per Phase-1 op:
Test plan
🤖 Generated with Claude Code