[VLSI26 Submission] SSTADEX Submission: Hierarchical Analog Design Exploration with One- and Two-Stage OTA Examples

[lild4d4]

This submission presents SSTADEX, a Python-based framework for structured and systematic analog design exploration built on symbolic analysis, lookup-table-driven transistor characterization, reusable primitives, and hierarchical macromodel composition.

Highlights

• Reusable LUT-based characterization workflow
• Primitive-level abstraction of analog circuit building blocks
• Hierarchical OTA construction using primitives and submacromodels
• Condition propagation and shared-node consistency across hierarchy levels
• One-stage and two-stage OTA design exploration examples
• Visualization and simulation-based verification of explored design points

Key Contribution
While our previous work introduced the underlying methodology, this submission delivers a newer and more solid software implementation through the SSTADEX Python library. The notebook serves as a practical and reproducible demonstration of how the framework can be applied to structured analog circuit design.

Reproducibility
The complete workflow is documented in the provided Jupyter notebook and can be reproduced using the included setup steps. The notebook was designed to run in Google Colab.

[atuchiya]

The files are created under ISSCC26 folder.
Please move them to VLSI26

[lild4d4]

Done, I moved them to VLSI26. Thanks for the heads up!