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Add LLM-Assisted Analog Amplifier Sizing — VLSI26 submission#185

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Add LLM-Assisted Analog Amplifier Sizing — VLSI26 submission#185
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LLM-Assisted Analog Amplifier Sizing — submission for the IEEE SSCS Code-a-Chip Travel Grant at VLSI 2026.

This notebook demonstrates an LLM-guided analog amplifier sizing flow on the SKY130 open-source PDK. It combines:

  • gm/ID methodology with pre-computed SKY130 look-up tables for physics-informed initial sizing
  • ngspice SPICE verification via a FastAPI simulation server (CircuitCollector) that auto-generates testbenches from Jinja2 templates
  • Iterative root-cause diagnosis using topology-specific skill files that Claude Code loads from .claude/skills/
  • Optional CMA-ES post-LLM refinement beyond the discrete LUT grid

The notebook sets up the full environment on a fresh Ubuntu/Debian system (ngspice 46 build from source, two conda envs, detached simulation server) and guides users to drive the interactive sizing flow from Claude Code in VS Code. Two historical run logs — Two-Stage Miller single-load OTA and 5-Transistor OTA with Sooch-style LV cascode load — are included as appendices to show the full 6-stage flow end-to-end, including extreme-PVT verification and CMA-ES optimization.

Supported topologies (production-ready): 5T OTA and Two-Stage Miller (TSM), each with single / cascode / wide-swing-cascode load variants. The sub-block black-box abstraction (5-quantity interface: gds_eq, C_eq, p_int, V_headroom, Vbias_ext) lets the same topology equations handle all nine structural combinations.

Team:

Name Affiliation IEEE SSCS
Jiyuan Duan Rice University Yes Yes
Shikai Wang George Washington University No No
Gerald Topalli Rice University Yes Yes
Houbo He Rice University Yes Yes
Lei Xia Rice University Yes Yes
Weidong Cao George Washington University Yes Yes
Taiyun Chi Rice University Yes Yes

Team lead (travel-grant recipient): Jiyuan Duan (jd200@rice.edu)

Source repo: https://github.com/jiyuanduan001-oss/LLM-Assisted-Analog-Amplifier-Sizing

Tools & versions:

  • ngspice 46 (built from source)
  • SKY130 open-source PDK
  • Python 3.11
  • Claude Code (latest, VS Code extension)
  • FastAPI 0.118+ (CircuitCollector simulation server)
  • Conda / Miniforge

Submission path: VLSI26/submitted_notebooks/LLM-Assisted_Analog_Amplifier_Sizing/

License: Apache 2.0

Jiyuan Duan and others added 2 commits April 14, 2026 14:47
Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
Submission for the IEEE SSCS Code-a-Chip Travel Grant at VLSI 2026.

Contents:
- LLM_Assisted_Analog_Amplifier_Sizing.ipynb — end-to-end environment setup
  (ngspice 46 build, two conda envs, CircuitCollector server) plus guidance
  to drive the interactive gm/ID sizing flow from Claude Code in VS Code.
  Includes a system-description appendix and two historical run logs
  (tsm_single, 5tota_lv_cascode) showing the full sizing + CMA-ES loop.
- README.md — team members, tool versions, repository link, references,
  Apache 2.0 license declaration.

Main source repo: https://github.com/jiyuanduan001-oss/LLM-Assisted-Analog-Amplifier-Sizing
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