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An Open-Source Digital Delay Locked Loop for Educational and Architectural Exploration#188

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An Open-Source Digital Delay Locked Loop for Educational and Architectural Exploration#188
ethanhuang03 wants to merge 5 commits into
sscs-ose:mainfrom
SiliconJackets:main

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This notebook serves as an interactive, supplementary resource for students learning about Delay-Locked Loops (DLLs). It explores several design variations of the key parts (submodules) of a DLL, specifically the Phase Detector, Controller, and Digitally Controlled Delay Line (DCDL). For each component, qualitative insights into behavior and design tradeoffs are paired with quantitative results received from SPICE simulations.

This exploration culminates in an interactive implementation of a practical DLL as a Zero-Delay Buffer (ZDB), presented through two complementary approaches:

  • A high-level Python model of each submodule derived from its SPICE-characterized behavior. This enables users to quickly swap between different design variants and observe their impact on overall system performance.
  • A parameterizable System Verilog (RTL) implementation in which users can tune key parameters within a selected submodule and modify its RTL-level behavior.

Simulating these changes allows users to view how design parameters influence the locking capabilities of the DLL. A Python interface additionally provides insights and feedback on the design choices made.

While Python-based simulations provide a fast and accessible way to explore the architectural trade-offs, RTL-level behavioral and SPICE simulations remain essential for identifying implementation-specific issues (glitches and race conditions) as well as parameter sensitivity (convergence behavior).

This design targets the open source sky130 PDK, a 130 nm CMOS process developed by Google and SkyWater Technology Foundry, supporting a fully open-source design flow from RTL through layout and fabrication.

Name Affiliation Email IEEE Member SSCS Member
Ethan Huang Georgia Institute of Technology ethanhuang@gatech.edu No No
Zheng-Yin Lee Georgia Institute of Technology zlee63@gatech.edu No No
Alfi Misha Antony Selvin Raj Georgia Institute of Technology alfiselvin@gatech.edu No No
Oliver S. Lee Georgia Institute of Technology xli3086@gatech.edu Yes No
Shreyas Angadi Georgia Institute of Technology sangadi6@gatech.edu No No
Mythri Muralikannan Georgia Institute of Technology mmuralikannan3@gatech.edu Yes Yes

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