An Open-Source Digital Delay Locked Loop for Educational and Architectural Exploration#188
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ethanhuang03 wants to merge 5 commits into
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An Open-Source Digital Delay Locked Loop for Educational and Architectural Exploration#188ethanhuang03 wants to merge 5 commits into
ethanhuang03 wants to merge 5 commits into
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This notebook serves as an interactive, supplementary resource for students learning about Delay-Locked Loops (DLLs). It explores several design variations of the key parts (submodules) of a DLL, specifically the Phase Detector, Controller, and Digitally Controlled Delay Line (DCDL). For each component, qualitative insights into behavior and design tradeoffs are paired with quantitative results received from SPICE simulations.
This exploration culminates in an interactive implementation of a practical DLL as a Zero-Delay Buffer (ZDB), presented through two complementary approaches:
Simulating these changes allows users to view how design parameters influence the locking capabilities of the DLL. A Python interface additionally provides insights and feedback on the design choices made.
While Python-based simulations provide a fast and accessible way to explore the architectural trade-offs, RTL-level behavioral and SPICE simulations remain essential for identifying implementation-specific issues (glitches and race conditions) as well as parameter sensitivity (convergence behavior).
This design targets the open source sky130 PDK, a 130 nm CMOS process developed by Google and SkyWater Technology Foundry, supporting a fully open-source design flow from RTL through layout and fabrication.