feat: implement specialized layout for decoupling capacitors

[sumithkumar07]

Specialized Decoupling Capacitor Layout Implementation

This PR addresses Issue #15 by implementing a specialized layout logic for decoupling capacitors to ensure they are placed in clean, logical rows near their respective main chips.

Changes Made

1. Enhanced Partitioning Logic

• Modified ChipPartitionsSolver to include a fallback detection method for decoupling capacitors. This ensures that even if metadata is missing, components with 2 pins on y+/y- sides that are strongly connected to complex chips are correctly identified.
• • Groups these capacitors into dedicated decoupling_caps partitions.

2. Specialized Inner Packing

• Implemented a custom layout engine within SingleInnerPartitionPackingSolver specifically for decoupling_caps partitions.
• • Instead of using a general-purpose packer, it now arranges capacitors in a deterministic, centered horizontal row with consistent spacing.

3. Global Packing Optimization

• Updated the global PartitionPackingSolver to use the shortest_connection_along_outline strategy. This prevents the capacitor groups from being placed directly on top of the main chip while maintaining high proximity.

Verification Results

Automated Tests

• Successfully ran RP2040Circuit.test.ts.
• • Verified that all capacitors are correctly identified and processed through the new specialized pipeline.

Visual Comparison (Theoretical)

• Before: Capacitors were scattered or clumped in a single block far from the chip.
• • After: Capacitors are aligned in clean rows, making the schematic much more readable and electrically intuitive.

[vercel]

@sumithkumar07 is attempting to deploy a commit to the tscircuit Team on Vercel.

A member of the Team first needs to authorize it.