Register Bank conflict fix#348
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Performance improvement
MNK = 32x32
Operand bank conflicts (TCU): 0x280 => 0x100
PERF: instrs=3088, cycles=10596, IPC=0.291
PERF: instrs=3088, cycles=9661, IPC=0.320
MNK = 128x128
Operand bank conflicts (TCU): 0xa000=>0x4000
PERF: instrs=142864, cycles=534563, IPC=0.267
PERF: instrs=142864, cycles=405638, IPC=0.352
The remaining conflicts are unavoidable
Request if you want the perf counter code
mx meta registers do not seem to be used in the current RTL, so either