Optimize xilinx_async_bram_patch.tcl#350
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This reduces the runtime complexity from O(x²) to O(x) by not searching through all cells when finding descendants.
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When running my Synthesis-to-Bitstream flow targeting a u250 FPGA, the runtime can get into the 100's of hours for large configurations. More than 90% of this time is spent running the xilinx_async_bram_patch.tcl script.
This patch reduces the runtime complexity from O(x²) to O(x) by not searching through all cells when finding descendants.
This reduces the worst case runtime by 94% from ~120 hours to ~7 for a 16 core 2 cluster configuration.
I do not have access to working FPGAs to test the generated bitstreams, but I verified my changes by running this modified version of the script on a wide range of configurations.
NB: This was not tested using Vortex's makefiles, but a modified version of Chipyards makefiles as a part of an attempt to run Vortex using FireSim, so results may vary.